A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-$muhbox m$CMOS

A clock and data recovery (CDR) architecture featuring a parallel phase detector is proposed for speeding up linear-type CDRs. A cause of speed limit in conventional CDRs is very short UP pulses in its phase detector circuit. The parallel phase detector expands UP pulsewidth by adding fixed-width using a half-rate clock. The parallel phase detector is used in the CDR with a couple of unbalanced charge-pump. The bandwidth of decision latches of the PD is extended by 1.7 times by using both shunt-peaking and capacitance coupling. The monolithic CDR implemented in 0.13-mum CMOS shows 1.7 times wider phase linear response region of 0.56UI than that of a conventional CDR. It operates at 12.5-Gb/s with PRBS 231-1 input data. Measurements show large jitter tolerance of over 0.5 UIpp for 4-8 MHz jitter frequency as well as jitter transfer characteristics independent on input-jitter amplitudes of 0.1, 0.3, and 0.5 UIpp

[1]  E. Mullner.  A 20 Gbit/s parallel phase detector and demultiplexer circuit in a production silicon bipolar technology with f/sub T/=25 GHz , 1996, Proceedings of the 1996 BIPOLAR/BiCMOS Circuits and Technology Meeting.

[2]  Stephen P. Boyd,et al.  Bandwidth extension in CMOS with optimized on-chip inductors , 2000, IEEE Journal of Solid-State Circuits.

[3]  B. Razavi,et al.  A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector , 2001, IEEE J. Solid State Circuits.

[4]  D. Friedman,et al.  A 0.18 /spl mu/m SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[5]  C.R. Hogge.  A self correcting clock recovery circuit , 1985, IEEE Transactions on Electron Devices.

[6]  B. Razavi,et al.  Analysis and modeling of bang-bang clock and data recovery circuits , 2004, IEEE Journal of Solid-State Circuits.

[7]  Muneo Fukaishi,et al.  A 6 Gbps CMOS phase detecting DEMUX module using half-frequency clock , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[8]  Behzad Razavi.  Clock Recovery from Random Binary Signals , 1996 .

[9]  Behzad Razavi,et al.  A 40 Gb/s clock and data recovery circuit in 0.18 μm CMOS technology , 2003 .

[10]  Y. Greshishchev,et al.  SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET application , 2000, IEEE Journal of Solid-State Circuits.

[11]  M. Meghelli,et al.  A 0.18 /spl mu/m SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[12]  T. Kawamura,et al.  A 12.5Gb/s CMOS BER test using a jitter-tolerant parallel CDR , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).