Low voltage and low power DLL-based frequency synthesizer for covering VHF frequency band

New architecture for a DLL based frequency synthesizer for wireless transceivers presents in this paper. This architecture has the advantages of occupy low area, low power, low voltage and low phase noise. DLLs are first ordered systems, so good stability can obtain in this design. This structure also can be used for generating fractional multiple of reference frequencies. The proposed circuit can operate at a substantially low supply voltage. As an example, the synthesizer is adopted to create the channel frequencies of French DVB-H/T standard. The circuit level and system level designs are presented. Also power consumption trade-offs are reported. It was shown that for the mentioned standard a mere 27 delay stages for VCDL is sufficient. Simulation results confirm the analytical predictions. The proposed DLL-based frequency synthesizer is implemented in a 0.13um CMOS technology.

[1]  G. Chien,et al.  A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications , 2000, IEEE Journal of Solid-State Circuits.

[2]  Venceslav F. Kroupa,et al.  Phase Lock Loops and Frequency Synthesis , 2003 .

[3]  M. Horowitz,et al.  Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[4]  Rong-Jyi Yang,et al.  Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  P. C. Maulik,et al.  A DLL-Based Programmable Clock Multiplier in 0.18-$\mu$ m CMOS With ${-}$70 dBc Reference Spur , 2007, IEEE Journal of Solid-State Circuits.

[6]  Behzad Razavi,et al.  Design of Analog CMOS Integrated Circuits , 1999 .

[7]  B.D. Unter Frequency synthesizers: Theory and design , 1979, Proceedings of the IEEE.

[8]  Tad A. Kwasniewski,et al.  A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[9]  Chih-Kong Ken Yang,et al.  A Comprehensive Delay Model for CMOS CML Circuits , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[10]  William J. Dally,et al.  A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips , 2002, IEEE J. Solid State Circuits.

[11]  Wonchan Kim,et al.  A dual-loop delay-locked loop using multiple voltage-controlled delay lines , 2001 .

[12]  Walid S. Saba,et al.  ANALYSIS AND DESIGN , 2000 .

[13]  P. R. Gray,et al.  A 900 MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications , 2000 .

[14]  Věnceslav F. Kroupa,et al.  Phase Lock Loops and Frequency Synthesis: Kroupa/Phase Lock Loops , 2005 .