Sparse FIR filters and the impact on FPGA area usage

In FIR filter design, a sparse filter is one that has a majority of zeros for coefficients. Generally, a sparse filter is designed in order to save area and speed up computations, but when implementing a sparse filter in an FPGA the expected area savings may not be realized. This paper shows that sparsity in an FIR filter does not generally translate directly into FPGA space (area) savings on a Virtex-4 FPGA.

[1]  Dan P. Scholnik.  A parallel digital architecture for delta-sigma modulation , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[2]  O. Gustafsson,et al.  On the Design of Sparse Half-Band Like FIR Filters , 2007, 2007 Conference Record of the Forty-First Asilomar Conference on Signals, Systems and Computers.

[3]  Charles D. Howard.  Minimizing FIR Filter Designs Implemented in FPGAs Utilizing Minimized Adder Graph Techniques , 2009 .

[4]  Dan P. Scholnik,et al.  Space-time vector delta-sigma modulation , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[5]  Jonathan Rose,et al.  Measuring the Gap Between FPGAs and ASICs , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Paul S. Zuchowski,et al.  A hybrid ASIC and FPGA architecture , 2002, ICCAD 2002.