Value locality based storage compression memory architecture for ECG sensor node

This paper proposes a value compression memory architecture for QRS detection in ultra-low-power ECG sensor nodes. Based on the exploration of value spatial locality in the most critical preprocessing stage of the ECG algorithm, a cost efficient compression strategy, which reorganizes several adjacent sample values into a base value with several displacements, is proposed. The displacements will be half or quarter scale quantifications; as a result, the storage size is reduced. The memory architecture saves memory space by storing compressed data with value spatial locality into a compressed memory section and by using a small, uncompressed memory section as backup to store the uncompressed data when a value spatial locality miss occurs. Furthermore, a low-power accession strategy is proposed to achieve low-power accession. An embodiment of the proposed memory architecture has been evaluated using the MIT/BIH database, the proposed memory architecture and a low-power accession strategy to achieve memory space savings of 32.5% and to achieve a 68.1% power reduction with a negligible performance reduction of 0.2%.

[1]  Daeyeon Kim,et al.  A Low-Voltage Processor for Sensing Applications With Picowatt Standby Mode , 2009, IEEE Journal of Solid-State Circuits.

[2]  David E. Culler,et al.  Telos: enabling ultra-low power wireless research , 2005, IPSN 2005. Fourth International Symposium on Information Processing in Sensor Networks, 2005..

[3]  Bert Gyselinckx,et al.  Human++: Wireless autonomous sensor technology for body area networks , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[4]  David Atienza,et al.  Wavelet-Based ECG Delineation on a Wearable Embedded Sensor Platform , 2009, 2009 Sixth International Workshop on Wearable and Implantable Body Sensor Networks.

[5]  G.B. Moody,et al.  PhysioNet: a Web-based resource for the study of physiologic signals , 2001, IEEE Engineering in Medicine and Biology Magazine.

[6]  Anantha Chandrakasan,et al.  An energy-efficient biomedical signal processing platform , 2010, 2010 Proceedings of ESSCIRC.

[7]  Gürhan Küçük,et al.  Reducing Energy Consumption of Wireless Sensor Networks through Processor Optimizations , 2007, J. Comput..

[8]  Rajit Manohar,et al.  An ultra low-power processor for sensor networks , 2004, ASPLOS XI.

[9]  David Blaauw,et al.  24.3 An implantable 64nW ECG-monitoring mixed-signal SoC for arrhythmia diagnosis , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[10]  Willis J. Tompkins,et al.  A Real-Time QRS Detection Algorithm , 1985, IEEE Transactions on Biomedical Engineering.

[11]  Feng Wan,et al.  A 0.83-$\mu {\rm W}$ QRS Detection Processor Using Quadratic Spline Wavelet Transform for Wireless ECG Acquisition in 0.35- $\mu{\rm m}$ CMOS , 2012, IEEE Transactions on Biomedical Circuits and Systems.

[12]  Refet Firat Yazicioglu,et al.  Ultra low power wireless ECG system with beat detection and real time impedance measurement , 2010, 2010 Biomedical Circuits and Systems Conference (BioCAS).

[13]  Mladen Berekovic,et al.  Design of 100 muW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring , 2007, SAMOS.

[14]  Jun Zhou,et al.  A 36μW heartbeat-detection processor for a wireless sensor node , 2011, TODE.

[15]  Naveen Verma,et al.  A 1.2–0.55V general-purpose biomedical processor with configurable machine-learning accelerators for high-order, patient-adaptive monitoring , 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).

[16]  Mladen Berekovic,et al.  Design of 100 μW Wireless Sensor Nodes for Biomedical Monitoring , 2009, J. Signal Process. Syst..

[17]  Pablo Laguna,et al.  A wavelet-based ECG delineator: evaluation on standard databases , 2004, IEEE Transactions on Biomedical Engineering.

[18]  Xiaojun Yuan,et al.  Multiple Functional ECG Signal is Processing for Wearable Applications of Long-Term Cardiac Monitoring , 2011, IEEE Transactions on Biomedical Engineering.

[19]  David Blaauw,et al.  A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution , 2005, CASES '05.

[20]  Ulrich Rückert,et al.  A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control , 2013, IEEE Journal of Solid-State Circuits.

[21]  Refet Firat Yazicioglu,et al.  A low power ECG signal processor for ambulatory arrhythmia monitoring system , 2010, 2010 Symposium on VLSI Circuits.

[22]  Bo Wang,et al.  A 457-nW cognitive multi-functional ECG processor , 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).

[23]  Mario Konijnenburg,et al.  A voltage-scalable biomedical signal processor running ECG using 13pJ/cycle at 1MHz and 0.4V , 2011, 2011 IEEE International Solid-State Circuits Conference.

[24]  Pierre Vandergheynst,et al.  Compressed Sensing for Real-Time Energy-Efficient ECG Compression on Wireless Body Sensor Nodes , 2011, IEEE Transactions on Biomedical Engineering.

[25]  Hoi-Jun Yoo,et al.  A Low Power 16-bit RISC with Lossless Compression Accelerator for Body Sensor Network System , 2006, 2006 IEEE Asian Solid-State Circuits Conference.

[26]  Alexander Fish,et al.  A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM) , 2011, IEEE Journal of Solid-State Circuits.

[27]  Refet Firat Yazicioglu,et al.  A 30 $\mu$ W Analog Signal Processor ASIC for Portable Biopotential Signal Monitoring , 2011, IEEE Journal of Solid-State Circuits.

[28]  Xin Liu,et al.  Power and Area Efficient Wavelet-Based On-chip ECG Processor for WBAN , 2010, 2010 International Conference on Body Sensor Networks.

[29]  Refet Firat Yazicioglu,et al.  A Configurable and Low-Power Mixed Signal SoC for Portable ECG Monitoring Applications , 2011, IEEE Transactions on Biomedical Circuits and Systems.