Partial Region and Bitstream Cost Models for Hardware Multitasking on Partially Reconfigurable FPGAs

Partial reconfiguration (PR) on field-programmable gate arrays (FPGAs) enables multiple PR modules (PRMs) to time multiplex partially reconfigurable regions (PRRs), which affords reduced reconfiguration time, area overhead, etc., as compared to non-PR systems. However, to effectively leverage PR, system designers must determine appropriate PRR sizes/organizations during early stages of PR system design, since inappropriate PRRs, given PRM requirements, can negate PR benefits, potentially resulting in system performance worse than a functionally-equivalent non-PR design. To aid in PR system design, we present two portable, high-level cost models, which are based on the synthesis report results generated by Xilinx tools. These cost models estimate PRR size/organization given the PRR's associated PRMs to maximize the PRRs' resource utilizations and estimate the PRM's associated partial bitstream sizes based on the PRR sizes/organizations. Experiments evaluate our cost models' accuracies for different PRMs and required resources, which enable our models to afford enhanced designer productivity since these models preclude the lengthy PR design flow, which is typically required to attain such analysis.

[1]  Bin Zhang,et al.  A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[2]  Ann Gordon-Ross,et al.  A one-shot dynamic optimization methodology for wireless sensor networks , 2010 .

[3]  Ann Gordon-Ross,et al.  HTR: On-Chip Hardware Task Relocation for Partially Reconfigurable FPGAs , 2013, ARC.

[4]  Ann Gordon-Ross,et al.  Lightweight runtime control flow analysis for adaptive loop caching , 2010, GLSVLSI '10.

[5]  Ann Gordon-Ross,et al.  On-chip Context Save and Restore of Hardware Tasks on Partially Reconfigurable FPGAs , 2013, 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines.

[6]  Ann Gordon-Ross,et al.  Low-Energy Instruction Cache Optimization Techniques for Embedded Systems , 2012, Handbook of Energy-Aware and Green Computing.

[7]  Axel Jantsch,et al.  Run-time Partial Reconfiguration speed investigation and architectural design space exploration , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[8]  Scott Hauck,et al.  Performance of partial reconfiguration in FPGA systems: A survey and a cost model , 2011, TRETS.

[9]  Ann Gordon-Ross,et al.  Dynamic Phase-Based Optimization of Embedded Systems , 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

[10]  François Duhem,et al.  Reconfiguration time overhead on field programmable gate arrays: reduction and cost model , 2012, IET Comput. Digit. Tech..

[11]  Luca Benini,et al.  Design Automation of Embedded Systems , 2003 .

[12]  Alan D. George,et al.  Smart-NICs: Power Proxying for Reduced Power Consumption in Network Edge Devices , 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

[13]  Dirk Koch,et al.  Partial Reconfiguration on FPGAs - Architectures, Tools and Applications , 2012, Lecture Notes in Electrical Engineering.