High Performance Quadrature Digital Mixers for FPGAs

This paper deals with the optimized implementation of high performance quadrature mixers for transmission. This work examines the most relevant architectures that may be used on FPGAs such as memory compression techniques and the CORDIC algorithm. Each technique is optimized for Virtex FPGAs in terms of area and throughput using relationally placed macros. In order to exploit the high-speed capabilities of these devices we have evaluated several VLSI architectural transforms and arithmetic techniques and we have identified which ones are still successful on FPGAs. We have applied the results of this study to the design of mixers attaining clock rates close to 280MHz.

[1]  H. Samueli,et al.  A 200 MHz quadrature digital synthesizer/mixer in 0.8 /spl mu/m CMOS , 1995 .

[2]  F. Cardells-Tormo,et al.  Optimisation of direct digital frequency synthesisers based on CORDIC , 2001 .

[3]  S. Tagzout,et al.  Compact parallel multipliers using the sign-generate method in FPGA , 1997, 1997 21st International Conference on Microelectronics. Proceedings.

[4]  Keshab K. Parhi,et al.  Evaluation of CORDIC Algorithms for FPGA Design , 2002, J. VLSI Signal Process..

[5]  Jack E. Volder.  The CORDIC Trigonometric Computing Technique , 1959, IRE Trans. Electron. Comput..

[6]  Mark Cummings,et al.  FPGA in the software radio , 1999, IEEE Commun. Mag..

[7]  Ray Andraka,et al.  A survey of CORDIC algorithms for FPGA based computers , 1998, FPGA '98.

[8]  Francisco Cardells-Tormo,et al.  Optimized FPGA-implementation of quadrature DDS , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[9]  Samir Tagzout,et al.  Compact parallel multipliers using the sign-generate method in FPGA , 1998 .

[10]  Keshab K. Parhi,et al.  A high-speed CORDIC algorithm and architecture for DSP applications , 1999, 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461).

[11]  Prof.Dr.-Ing. Ulrich Reimers.  Digital Video Broadcasting (DVB) , 2001, Springer Berlin Heidelberg.

[12]  Jouko Vankka.  1996 IEEE INTERNATIONAL FREQUENCY CONTROL SYMPOSIUM METHODS OF MAPPING FROM PHASE TO SINE AMPLITUDE IN DIRECT DIGITAL SYNTHESIS , 1996 .

[13]  A. Y. Kwentus,et al.  A 100-MHz, 16-b, direct digital frequency synthesizer with a 100-dBc spurious-free dynamic range , 1999, IEEE J. Solid State Circuits.

[14]  H. Samueli,et al.  The optimization of direct digital frequency synthesizer performance in the presence of finite word length effects , 1988, Proceedings of the 42nd Annual Frequency Control Symposium, 1988..

[15]  Chris Dick,et al.  Configurable logic for digital communications: some signal processing perspectives , 1999, IEEE Commun. Mag..

[16]  Gerhard Fettweis,et al.  The digital front-end of software radio terminals , 1999, IEEE Wirel. Commun..

[17]  R. J. van de Plassche,et al.  A 540-MHz 10-b polar-to-Cartesian converter , 1991 .

[18]  H. Samueli,et al.  A 150-MHz Direct Digital Frequency Synthesizer In 1.25/spl mu/m CMOS With -90dBc Spurious Performance , 1991 .

[19]  J. S. Walther,et al.  A unified algorithm for elementary functions , 1899, AFIPS '71 (Spring).

[20]  B. Gold,et al.  A digital frequency synthesizer , 1971 .

[21]  Gerhard Fettweis,et al.  Digital down conversion in software radio terminals , 2000, 2000 10th European Signal Processing Conference.

[22]  C. R. Cole,et al.  CMOS/SOS frequency synthesizer LSI circuit for spread spectrum communications , 1984 .

[23]  Ernest Jamro,et al.  Implementation of multipliers in FPGA structures , 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.