ARET for system-level IC reliability simulation

The simulator ARET (ASIC Reliability Evaluation Tool) is being developed at Georgia Institute of Technology. ARET focuses on system-level reliability with several efficient built-in system-level simulation models. By developing ARET, we are trying to focus on "real world" ICs - ICs with fabrication defects in devices and interconnect - and simulate IC reliability from a system perspective to accomplish design-for-reliability. As the basis of system-level simulation, device-level failure models incorporating physical defects were created and checked with measured data. To accurately evaluate the reliability at system-level, several simulation models were developed by means of circuit simulation, hierarchical analyses and statistical approaches.