STA compatible backend design flow for TSV-based 3-D ICs

In the era of post-device scaling, three-dimensional (3-D) integration is a promising solution to meet performance, power, and cost requirements in modern applications, such as IoT, high performance computing, and cyber-physical systems. A novel design automation flow, compatible with static timing analysis (STA), for exploring the timing and power of 3-D ICs is proposed. Among the different types of vertical interconnects, TSVs modeled as RC wires, are considered in this work. The flow enables design space exploration and optimization utilizing existing timing and power analysis tools, e.g. PrimeTime and PrimeTimePX. The design experience is similar to a 2-D design flow where the placement in multiple tiers is merely performed by an open-source 3-D placer. Application of the flow to different benchmark circuits shows that even with no optimization effort, a two tier 3-D stack produced by the flow achieves up to 14.6% average power reduction, 18.7% performance improvement, and 49% footprint reduction as compared to the 2-D design for a specific circuit.