A Pipelined 330 MHz Multiplier

An 8 × 8 bit NMOS multiplier test chip for image processing systems has been realized on the basis of a newly designed carry save adder cell, a multiplication rate of 3.3 108 1/sec (fc = 330 MHz) being achieved.

[1]  S.L. Freeny,et al.  Special-purpose hardware for digital filtering , 1975, Proceedings of the IEEE.

[2]  J. Deverell.  Pipeline Iterative Arithmetic Arrays , 1975, IEEE Transactions on Computers.

[3]  Sudhir Ahuja,et al.  Effective Pipelining of Digital Systems , 1978, IEEE Transactions on Computers.

[4]  H. T. Kung.  Why systolic architectures? , 1982, Computer.

[5]  John G. McWhirter,et al.  Completely iterative, pipelined multiplier array suitable for VLSI , 1982 .

[6]  E.N. Fuls,et al.  A Fine-Line nMOS IC for Raster-Scan Control of a 500-MHz Electron-Beam Deflection System , 1982, IEEE Journal of Solid-State Circuits.