Design and implementation of a switched capacitor-based embedded hybrid DC–DC converter

Here, we propose an integrated hybrid DC–DC converter suitable for high drop-out energy conscious applications. In the hybrid converter topology, along with a linear regulator two switched capacitors are used to store and recycle charge for better power efficiency. Without significant power loss the switched capacitors step down the supply voltage for the linear regulator working in low drop-out mode. The linear regulator, on the other hand, attenuates the voltage ripple that originates from the switched capacitors converter on its power supply rejection ratio. It also helps for line and load regulation. Additionally, a synthesised counter ripple is injected through the linear regulator to further reduce the output ripple. With these two techniques, for a moderate load current and an acceptable output ripple, the switching and load capacitors are reduced to a value which can be implemented within the chip. The proposed integrated converter circuit has been designed, implemented and tested in a 0.18 mm CMOS process for 3.3–1.3V conversion. With two switching capacitors of 210 pF each and 100 pF load capacitor, more than 13 mA of load current, measured peak-to-peak output voltage ripple is 146 mV. The achieved measured power efficiency is 64.97%. Exhaustive silicon characterisation of the converter is done to observe the power efficiency and ripple variation at different frequency of operations.

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