A Low Speed Digital Correlator Architecture Optimized For Resource Savings

In this paper we present a new implementation of correlation algorithm and its application in anti-collision radar system. Our architecture focuses on resource saving while reducing the processing speed as required by our application specifications. A scaled down prototype of the proposed architecture was first implemented, tested and verified. Then a full scale system was designed and implemented in FPGA. Experimental results showed that complexity of the resulting circuit has been reduced by a factor of 5. The work presented in this article is carried out in the framework of a TACT project RaViOLi (Radar et Vision Orientable, Lidar) aimed at the development of intelligent vehicles.