Ternary and quaternary lattice diagrams for linearly-independent logic, multiple-valued logic, and analog synthesis

Ternary and quaternary lattice diagrams are introduced that can find applications to submicron design, and designing new fine-grain digital, analog and mixed FPGAs. They expand the ideas of lattice diagrams and linearly-independent (LI) logic. In a regular layout, every cell is connected to 4, 6 or 8 neighbors and to a number of vertical, horizontal and diagonal buses. Various lattices and algorithms for their creation are presented.

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