Skewed-Load Transition Test: Part I, Calculus
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[1] Jacob Savir,et al. AT-SPEED TEST IS NOT NECESSARILY AN AC TEST , 1991, 1991, Proceedings. International Test Conference.
[2] Prabhakar Goel,et al. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.
[3] Barry K. Rosen,et al. Comparison of AC Self-Testing Procedures , 1983, ITC.
[4] Orest Bula,et al. Gross delay defect evaluation for a CMOS logic design system product , 1990 .
[5] J. Savir. Improved cutting algorithm , 1990 .
[6] Jr. Sheldon B. Akers,et al. On a Theory of Boolean Functions , 1959 .
[7] Irving S. Reed,et al. Path Sensitization, Partial Boolean Difference, and Automated Fault Diagnosis , 1972, IEEE Transactions on Computers.
[8] Thomas W. Williams,et al. A logic design structure for LSI testability , 1977, DAC '77.
[9] Gordon L. Smith,et al. Model for Delay Faults Based upon Paths , 1985, ITC.
[10] Jacob Savir,et al. On Random Pattern Test Length , 1984, IEEE Transactions on Computers.
[11] John A. Waicukauski,et al. On computing the sizes of detected delay faults , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[12] Edward J. McCluskey,et al. Probabilistic Treatment of General Combinational Networks , 1975, IEEE Transactions on Computers.
[13] Gary S. Ditlow,et al. Random Pattern Testability , 1984, IEEE Transactions on Computers.
[14] Jacob Savir,et al. Random Pattern Testability of Delay Faults , 1988, IEEE Trans. Computers.