Design of High-Speed and Power-Efficient Ternary Prefix Adders Using CNFETs
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[1] Jörg Appenzeller,et al. Carbon Nanotubes for High-Performance Electronics—Progress and Prospect , 2008, Proceedings of the IEEE.
[2] H. T. Mouftah,et al. Depletion/enhancement CMOS for a lower power family of three-valued logic circuits , 1985 .
[3] Masao Mukaidono. Regular Ternary Logic Functions—Ternary Logic Functions Suitable for Treating Ambiguity , 1986, IEEE Transactions on Computers.
[4] K. Sridharan,et al. Efficient Multiternary Digit Adder Design in CNTFET Technology , 2013, IEEE Transactions on Nanotechnology.
[5] Yong-Bin Kim,et al. CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits , 2011, IEEE Transactions on Nanotechnology.
[6] Chetan Vudadha,et al. CNFET based ternary magnitude comparator , 2012, 2012 International Symposium on Communications and Information Technologies (ISCIT).
[7] Tack-Don Han,et al. Fast area-efficient VLSI adders , 1987, 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH).
[8] Andreas Antoniou,et al. Low power dissipation MOS ternary logic family , 1984 .
[9] Li Wei,et al. (n,m) Selectivity of single-walled carbon nanotubes by different carbon precursors on Co-Mo catalysts. , 2007, Journal of the American Chemical Society.
[10] F. Lombardi,et al. A novel CNTFET-based ternary logic gate design , 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.
[11] David Harris,et al. A taxonomy of parallel prefix networks , 2003, The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003.
[12] K. Sridharan,et al. Carbon nanotube FET-based low-delay and low-power multi-digit adder designs , 2017, IET Circuits Devices Syst..
[13] MahyarShahsavari. Low Power CNTFET-Based Ternary Full Adder Cell for Nanoelectronics , 2012 .
[14] Anu Gupta,et al. Design of High Speed Ternary Full Adder and Three-Input XOR Circuits Using CNTFETs , 2015, 2015 28th International Conference on VLSI Design.
[15] Anu Gupta,et al. Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology , 2015 .
[16] K. Roy,et al. Carbon-nanotube-based voltage-mode multiple-valued logic design , 2005, IEEE Transactions on Nanotechnology.
[17] Harold S. Stone,et al. A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.
[18] Keivan Navi,et al. High-Efficient Circuits for Ternary Addition , 2014, VLSI Design.
[19] Fabrizio Lombardi,et al. Design and Evaluation of Multiple Valued Logic Gates Using Pseudo N-Type Carbon Nanotube FETs , 2014, IEEE Transactions on Nanotechnology.
[20] Peiman Keshavarzian,et al. A Novel CNTFET-based Ternary Full Adder , 2014, Circuits Syst. Signal Process..
[21] H. T. Kung,et al. A Regular Layout for Parallel Adders , 1982, IEEE Transactions on Computers.
[22] Yutaka Ohno,et al. Chirality assignment of individual single-walled carbon nanotubes in carbon nanotube field-effect transistors by micro-photocurrent spectroscopy , 2004 .
[23] T. Nakamura,et al. Realization of quaternary logic circuits by n-channel MOS devices , 1986 .
[24] David A. Rich,et al. A Survey of Multivalued Memories , 1986, IEEE Transactions on Computers.
[25] H. Wong,et al. A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region , 2007, IEEE Transactions on Electron Devices.
[26] Chetan Vudadha,et al. An Efficient Design Methodology for CNFET Based Ternary Logic Circuits , 2016, 2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS).