Highly accurate SPICE-compatible modeling for single- and double-gate GNRFETs with studies on technology scaling

In this paper, we present a highly accurate closed-form compact model for Schottky-Barrier-type Graphene Nano-Ribbon Field-Effect Transistors (SB-GNRFETs). This is a physics-based analytical model for the current-voltage (I-V) characteristics of SB-GNRFETs. We carry out accurate approximations of Schottky barrier tunneling, channel charge and current, which provide improved accuracy while maintaining compactness. This SPICE-compatible compact model surpasses the existing model [15] in accuracy, and enables efficient circuit-level simulations of futuristic GNRFET-based circuits. The proposed model considers various design parameters and process variation effects, including graphene-specific edge roughness, which allows complete and thorough exploration and evaluation of SB-GNRFET circuits. We are able to model both single- and double-gate SB-GNRFETs, so we can evaluate and compare these two types of SB-GNRFET. We also compare circuit-level performance of SB-GNRFETs with multi-gate (MG) Si-CMOS for a scalability study in future generation technology. Our circuit simulations indicate that SB-GNRFET has an energy-delay product (EDP) advantage over Si-CMOS; the EDP of the ideal SB-GNRFET (assuming no process variation) is ~1.3% of that of Si-CMOS, while the EDP of the non-ideal case with process variation is 136% of that of Si-CMOS. Finally, we study technology scaling with SB-GNRFET and MG Si-CMOS. We show that the EDP of ideal (non-ideal) SB-GNRFET is ~0.88% (54%) EDP of that of Si-CMOS as the technology nodes scales down to 7 nm.

[1]  Ying-Yu Chen,et al.  Schottky-barrier-type Graphene Nano-Ribbon Field-Effect Transistors: A study on compact modeling, process variation, and circuit performance , 2013, 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

[2]  Max C. Lemme,et al.  An integration approach for graphene double-gate transistors , 2012, 2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

[3]  Yu Cao,et al.  Exploring sub-20nm FinFET design with Predictive Technology Models , 2012, DAC Design Automation Conference 2012.

[4]  S. Santucci,et al.  Large area extreme-UV lithography of graphene oxide via spatially resolved photoreduction. , 2012, Langmuir : the ACS journal of surfaces and colloids.

[5]  G. Dambrine,et al.  Flexible gigahertz transistors derived from solution-based single-layer graphene. , 2012, Nano letters.

[6]  U. Schwalke,et al.  Transfer-free fabrication of graphene transistors , 2011, 1112.4320.

[7]  Jing Guo,et al.  Graphene Nanoribbon FETs: Technology Exploration for Performance and Reliability , 2011, IEEE Transactions on Nanotechnology.

[8]  Giuseppe Iannaccone,et al.  Semi-analytical model for schottky-barrier carbon nanotube and graphene nanoribbon transistors , 2010, GLSVLSI '10.

[9]  H. Dai,et al.  Aligned graphene nanoribbons and crossbars from unzipped carbon nanotubes , 2010, 1004.5392.

[10]  G. Iannaccone,et al.  Analytical Model of One-Dimensional Carbon-Based Schottky-Barrier Transistors , 2009, IEEE Transactions on Electron Devices.

[11]  H. Dai,et al.  Room-temperature all-semiconducting sub-10-nm graphene nanoribbon field-effect transistors. , 2008, Physical review letters.

[12]  D. Jiménez A current–voltage model for Schottky-barrier graphene-based transistors , 2007, Nanotechnology.

[13]  H. Wong,et al.  A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region , 2007, IEEE Transactions on Electron Devices.

[14]  G. Fiori,et al.  Simulation of Graphene Nanoribbon Field-Effect Transistors , 2007, IEEE Electron Device Letters.

[15]  P. Kim,et al.  Energy band-gap engineering of graphene nanoribbons. , 2007, Physical review letters.

[16]  M. Rooks,et al.  Graphene nano-ribbon electronics , 2007, cond-mat/0701599.

[17]  S. Louie,et al.  Energy gaps in graphene nanoribbons. , 2006, Physical review letters.

[18]  C. Berger,et al.  Electronic Confinement and Coherence in Patterned Epitaxial Graphene , 2006, Science.

[19]  A. Rinzler,et al.  An Integrated Logic Circuit Assembled on a Single Carbon Nanotube , 2006, Science.

[20]  Rui Zhang,et al.  Synthesis and optimization of threshold logic networks with application to nanotechnologies , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[21]  J. Maultzsch,et al.  Tight-binding description of graphene , 2002 .

[22]  John W. Mintmire,et al.  Universal Density of States for Carbon Nanotubes , 1998 .

[23]  Fujita,et al.  Edge state in graphene ribbons: Nanometer size effect and edge shape dependence. , 1996, Physical review. B, Condensed matter.

[24]  N. Frank,et al.  Transmission of Electrons through Potential Barriers , 1931 .

[25]  Benjamin M. Fitzgerald Transistors : types, materials, and applications , 2010 .

[26]  G. Fiori,et al.  Code for the 3D Simulation of Nanoscale Semiconductor Devices, Including Drift-Diffusion and Ballistic Transport in 1D and 2D Subbands, and 3D Tunneling , 2004, 2004 Abstracts 10th International Workshop on Computational Electronics.