Compaction schemes with minimum test application time

Testing embedded cores in a System-On-a-Chip (SoC) necessitates the use of a test access mechanism, which provides for transportation of the test data between the chip and the core I/Os. To relax the requirements on the test access mechanism at the core output side, we outline a space and time compaction scheme which minimizes test application time and required test bandwidth at the same time. We formulate the constraints on a mathematical basis for no aliasing compaction circuitry. The proposed compaction scheme is applicable to both combinational and sequential circuits. The experimental results illustrate that not only test application time is minimized but furthermore the associated area overhead is low as well.

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