Lazy Spilling for a Time-Predictable Stack Cache: Implementation and Analysis

The growing complexity of modern computer architectures increasingly complicates the prediction of the run-time behavior of software. For real-time systems, where a safe estimation of the program's worst-case execution time is needed, time-predictable computer architectures promise to resolve this problem. A stack cache, for instance, allows the compiler to efficiently cache a program's stack, while static analysis of its behavior remains easy. Likewise, its implementation requires little hardware overhead. This work introduces an optimization of the standard stack cache to avoid redundant spilling of the cache content to main memory, if the content was not modified in the meantime. At first sight, this appears to be an average-case optimization. Indeed, measurements show that the number of cache blocks spilled is reduced to about 17% and 30% in the mean, depending on the stack cache size. Furthermore, we show that lazy spilling can be analyzed with little extra effort, which benefits the worst-case spilling behavior that is relevant for a real-time system.

[1]  Benedikt Huber,et al.  Data cache organization for accurate timing analysis , 2012, Real-Time Systems.

[2]  Martin Schoeberl,et al.  Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach , 2011, PPES.

[3]  Martin Schoeberl,et al.  Static analysis of worst-case stack cache behavior , 2013, RTNS '13.

[4]  Reinhold Heckmann,et al.  Static Memory and Timing Analysis of Embedded Systems Code , 2006 .

[5]  Edward A. Lee,et al.  PRET DRAM controller: Bank privatization for predictability and temporal isolation , 2011, 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[6]  Martin Schoeberl,et al.  A time-predictable stack cache , 2013, 16th IEEE International Symposium on Object/component/service-oriented Real-time distributed Computing (ISORC 2013).

[7]  Trevor Mudge,et al.  MiBench: A free, commercially representative embedded benchmark suite , 2001 .

[8]  Soonhoi Ha,et al.  A Novel Technique to Use Scratch-pad Memory for Stack Management , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[9]  David B. Whalley,et al.  Timing analysis for data caches and set-associative caches , 1997, Proceedings Third IEEE Real-Time Technology and Applications Symposium.

[10]  Jan Reineke,et al.  Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  M. Smelyanskiy,et al.  Stack value file: custom microarchitecture for the stack , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

[12]  Reinhard Wilhelm,et al.  Efficient and Precise Cache Behavior Prediction for Real-Time Systems , 1999, Real-Time Systems.