A Novel Technique to Design Energy-Efficient Contexts for Reconfigurable Logic Devices
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[1] Steven J. E. Wilton,et al. A detailed power model for field-programmable gate arrays , 2005, TODE.
[2] Takayuki Sugawara,et al. Dynamically Reconfigurable Processor Implemented with IPFlex's DAPDNA Technology , 2004, IEICE Trans. Inf. Syst..
[3] Jason Cong,et al. FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[4] Iida Masahiro,et al. A Low-Power Technique using Resource Sharing Approach for Multi-Context Device , 2006 .
[5] Masahiro Iida,et al. A low power design method using multi-context dynamic reconfiguration , 2005 .
[6] Shekhar Y. Borkar,et al. Low power design challenges for the decade (invited talk) , 2001, ASP-DAC '01.
[7] Shoji Yamamoto,et al. Data Dependent Circuit for Subgraph Isomorphism Problem , 2002, FPL.
[8] Jason Cong,et al. Cut ranking and pruning: enabling a general and efficient FPGA mapping solution , 1999, FPGA '99.