A 10-bit piplined A/D converter with split calibration and opamp-sharing technique

A digital calibration technique based on the split-ADC is proposed to correct linear gain errors in a 10-bit pipelined A/D converter, which allows the use of low-gain amplifiers in conversion stages. Fabricated in a 0.35-µm CMOS technology, the core area of the ADC occupies 1.64 mm2. The opamp-sharing technique helps to reduce the core power consumption to 45 mW from a 3-V supply voltage at 50 MS/s. The SNDR and the SFDR of the calibrated output exhibit 55.2 dB and 67.0 dB, respectively. The proposed calibration system converges in less than 5×105 cycles.