论文信息 - Speed-area trade-off for 10 to 100 Gbits/s throughput AES processor

Speed-area trade-off for 10 to 100 Gbits/s throughput AES processor

This paper explores the area-throughput trade-off for an ASIC implementation of the advanced encryption standard (AES) algorithm in a 0.18 /spl mu/m CMOS technology. Three different pipelined implementations of the AES algorithm are presented which provide a throughput range between 15.7 to 77.6 Gbits/s with an area cost of 116 to 473 Kgates. Therefore, the AES algorithm in the counter mode of operation can be used to generate cryptographically secure pseudorandom numbers at a throughput rate of multiten Gbits/s. Thus it becomes available for encryption on an optical link.

Ingrid Verbauwhede | A. Hodjat

[1] Christof Paar,et al. An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[2] Elisabeth Oswald,et al. An ASIC Implementation of the AES SBoxes , 2002, CT-RSA.

[3] Kris Gaj,et al. Fast Implementation and Fair Comparison of the Final Candidates for Advanced Encryption Standard Using Field Programmable Gate Arrays , 2001, CT-RSA.

[4] Patrick Schaumont,et al. Design and performance testing of a 2.29-GB/s Rijndael processor , 2003, IEEE J. Solid State Circuits.

[5] Mitsuru Matsui,et al. Hardware Evaluation of the AES Finalists , 2000, AES Candidate Conference.

[6] Akashi Satoh,et al. A Compact Rijndael Hardware Architecture with S-Box Optimization , 2001, ASIACRYPT.

[7] Máire O'Neill,et al. High Performance Single-Chip FPGA Rijndael Algorithm Implementations , 2001, CHES.

[8] Patrick Schaumont,et al. A 2.29 Gbits/sec, 56 mW non-pipelined Rijndael AES encryption IC in a 1.8 V, 0.18 /spl mu/m CMOS technology , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).