An architecture and design tool flow for embedding a virtual FPGA into a reconfigurable system-on-chip

Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved.

[1]  Marco Platzner,et al.  ReconOS: Multithreaded programming for reconfigurable computers , 2009, TECS.

[2]  Guy Lemieux,et al.  ZUMA: An Open FPGA Overlay Architecture , 2012, 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines.

[3]  Douglas L. Maskell,et al.  Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq , 2016, SIGARCH Comput. Archit. News.

[4]  Marco Platzner,et al.  Embedding FPGA overlays into configurable Systems-on-Chip: ReconOS meets ZUMA , 2014, 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14).

[5]  Lukás Sekanina.  Virtual Reconfigurable Circuits for Real-World Applications of Evolvable Hardware , 2003, ICES.

[6]  Steven J. E. Wilton,et al.  Architectures and algorithms for field-programmable gate arrays with embedded memory , 1997 .

[7]  Gordon J. Brebner,et al.  The swappable logic unit: a paradigm for virtual hardware , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[8]  Jürgen Becker,et al.  A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture , 2011, 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum.

[9]  Kenneth B. Kent,et al.  The VTR project: architecture and CAD for FPGAs from verilog to routing , 2012, FPGA '12.

[10]  Marco Platzner,et al.  On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach , 2015, ARC.

[11]  Marco Platzner,et al.  Virtualization of Hardware - Introduction and Survey , 2004, ERSA.

[12]  Marco Platzner,et al.  Memory security in reconfigurable computers: Combining formal verification with monitoring , 2014, 2014 International Conference on Field-Programmable Technology (FPT).

[13]  Vincenzo Piuri,et al.  Virtual FPGAs: Some Steps Behind the Physical Barriers , 1998, IPPS/SPDP Workshops.

[14]  Hugo De Man,et al.  A hardware virtual machine for networked reconfiguration , 2000, Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype (Cat. No.PR00668).

[15]  Dominique Lavenier,et al.  Placing, Routing, and Editing Virtual FPGAs , 2001, FPL.

[16]  Frank Vahid,et al.  Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only) , 2005, FPGA '05.

[17]  Marco Platzner,et al.  ReconOS: An Operating System Approach for Reconfigurable Computing , 2014, IEEE Micro.

[18]  James Coole,et al.  Intermediate fabrics: Virtual architectures for circuit portability and fast placement and routing , 2010, 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[19]  Moritoshi Yasunaga,et al.  Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA , 2007, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007).