Fully Integrated Capacitive DC–DC Converter With All-Digital Ripple Mitigation Technique

This paper presents an adaptive all-digital ripple mitigation technique for fully integrated capacitive dc-dc converters. Ripple control is achieved using a two-pronged approach where coarse ripple control is achieved by varying the size of the bucket capacitance, and fine control is achieved by charge/discharge time modulation of the bucket capacitors used to transfer the charge between the input and output, both of which are completely digital techniques. A dual-loop control was used to achieve regulation and ripple control. The primary single-bound hysteretic control loop achieves voltage regulation and the secondary loop is responsible for ripple control. The dual-loop control modulates the charge/discharge pulse width in a hysteretic variable-frequency environment using a simple digital pulse width modulator. The fully integrated converter was implemented in IBM's 130-nm CMOS process. Ripple reduces from 98 to 30 mV, when ripple control secondary loop is enabled for a load of 0.3 V and 4 mA without significantly impacting the converter's core efficiency. Measurement results show constant ripple, independent of output voltage. The converter achieves a maximum efficiency of 70% for Vin= 1.3 V and Vout= 0.5 V and a maximum power density of 24.5 mW/mm2, including the areas for the decoupling capacitor. The maximum power density increases to 68 mW/mm2 if the decoupling capacitor is assumed to be already present as part of the digital design.

[1]  R. Harjani,et al.  A High-Efficiency DC–DC Converter Using 2 nH Integrated Inductors , 2008, IEEE Journal of Solid-State Circuits.

[2]  Elad Alon,et al.  Design Techniques for Fully Integrated Switched-Capacitor DC-DC Converters , 2011, IEEE Journal of Solid-State Circuits.

[3]  Hoi Lee,et al.  An SC Voltage Doubler with Pseudo-Continuous Output Regulation Using a Three-Stage Switchable Opamp , 2007, IEEE Journal of Solid-State Circuits.

[4]  T. Karnik,et al.  Area-efficient linear regulator with ultra-fast load regulation , 2005, IEEE Journal of Solid-State Circuits.

[5]  R.W. Brodersen,et al.  A dynamic voltage scaled microprocessor system , 2000, IEEE Journal of Solid-State Circuits.

[6]  Ramesh Harjani,et al.  Fully integrated on-chip DC-DC converter with a 450x output range , 2010, IEEE Custom Integrated Circuits Conference 2010.

[7]  Kaushik Roy,et al.  A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[8]  Ramesh Harjani,et al.  Capacitive voltage multipliers: a high efficiency method to generate multiple on-chip supply voltages , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[9]  A.P. Chandrakasan,et al.  Ultra-dynamic Voltage scaling (UDVS) using sub-threshold operation and local Voltage dithering , 2006, IEEE Journal of Solid-State Circuits.

[10]  R. Divakaruni,et al.  A novel, low-cost deep trench decoupling capacitor for high-performance, low-power bulk CMOS applications , 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

[11]  Yu Pu.  An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage , 2010 .

[12]  R. Dennard,et al.  A fully-integrated switched-capacitor 2∶1 voltage converter with regulation capability and 90% efficiency at 2.3A/mm2 , 2010, 2010 Symposium on VLSI Circuits.

[13]  Anantha Chandrakasan,et al.  A Fully-Integrated Switched-Capacitor Step-Down DC-DC Converter With Digital Capacitance Modulation in 45 nm CMOS , 2010, IEEE Journal of Solid-State Circuits.