Design of a Nanometric CMOS Memory Cell for Hardening to a Single Event With a Multiple-Node Upset

Nanometric CMOS is likely to experience the occurrence of a single event causing a multiple-node upset. This paper presents a novel memory cell design as variant of the DICE cell (that is tolerant to only a single event with a single-node upset). The proposed design is referred to as TDICE and uses transistors to block the paths that connect a node to the next node in the feedback loop of the memory cell circuit. The use of these transistors hardens the cell to tolerate a single event with a multiple-node upset at a large value of critical charge. Extensive simulation results are provided to assess TDICE with respect to traditional circuit figures of merit such as area, power consumption, and delay as well as PVT variations. The simulation results show that, at the expense of an increased area for the additional transistors, TDICE shows a nearly complete tolerance to a single event with a multiple-node upset.

[1]  G. C. Messenger,et al.  Collection of Charge on Junction Nodes from Ion Tracks , 1982, IEEE Transactions on Nuclear Science.

[2]  Resve Saleh,et al.  Simulation and analysis of transient faults in digital circuits , 1992 .

[3]  S. Whitaker,et al.  Low power SEU immune CMOS memory circuits , 1992 .

[4]  T. Calin,et al.  Upset hardened memory design for submicron CMOS technology , 1996 .

[5]  C. Detcheverry,et al.  SEU critical charge and sensitive area in a submicron CMOS technology , 1997 .

[6]  P. Hazucha,et al.  Impact of CMOS technology scaling on the atmospheric neutron soft error rate , 2000 .

[7]  R. Baumann.  Soft errors in advanced semiconductor devices-part I: the three radiation sources , 2001 .

[8]  Lloyd W. Massengill,et al.  Basic mechanisms and modeling of single-event upset in digital microelectronics , 2003 .

[9]  B.L. Bhuva,et al.  Charge Collection and Charge Sharing in a 130 nm CMOS Technology , 2006, IEEE Transactions on Nuclear Science.

[10]  A.F. Witulski,et al.  Directional Sensitivity of Single Event Upsets in 90 nm CMOS Due to Charge Sharing , 2007, IEEE Transactions on Nuclear Science.

[11]  Chenming Hu,et al.  Statistical Compact Modeling of Variations in Nano MOSFETs , 2008, 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

[12]  Yong-Bin Kim,et al.  Soft-Error Hardening Designs of Nanoscale CMOS Latches , 2009, 2009 27th IEEE VLSI Test Symposium.

[13]  Shi-Jie Wen,et al.  Effects of multi-node charge collection in flip-flop designs at advanced technology nodes , 2010, 2010 IEEE International Reliability Physics Symposium.

[14]  Yong-Bin Kim,et al.  Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset , 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

[15]  P. Reviriego,et al.  Enhanced Detection of Double and Triple Adjacent Errors in Hamming Codes Through Selective Bit Placement , 2012, IEEE Transactions on Device and Materials Reliability.