A Process Algebraic View of Latency-Insensitive Systems

Latency-insensitive (LI) systems are those which can function correctly in spite of delays along its connecting wires. This delay is assumed to be a multiple of the clock period. The paper presents a single-clock process algebraic model for such systems. It gives the definitions for LI computational blocks and LI connectors. Important properties for these are shown to be satisfied. Composition of such modules can be done by the parallel composition operator of the process algebra. Conditions are given to check for liveness and deadlock freedom of LI systems. Comparison of latency equivalence between streams of events can be done using the model and this leads to a method of proving latency-equivalent modules. The paper is a step toward high-level specification and verification of such systems. The work can be extended to address more complex interconnections by modeling the underlying finite-state machines.

[1]  Sandeep K. Shukla,et al.  Validating Families of Latency Insensitive Protocols , 2005, IEEE Transactions on Computers.

[2]  Joseph Sifakis,et al.  The Algebra of Timed Processes, ATP: Theory and Application , 1994, Inf. Comput..

[3]  Robin Milner,et al.  Communication and concurrency , 1989, PHI Series in computer science.

[4]  Yervant Zorian,et al.  2001 Technology Roadmap for Semiconductors , 2002, Computer.

[5]  Luca P. Carloni,et al.  Design, Implementation, and Validation of a New Class of Interface Circuits for Latency-Insensitive Design , 2007, 2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007).

[6]  Paul Le Guernic,et al.  An algebraic theory for behavioral modeling and protocol synthesis in system design , 2006, Formal Methods Syst. Des..

[7]  Amir Pnueli,et al.  Marked Directed Graphs , 1971, J. Comput. Syst. Sci..

[8]  Andrew William Roscoe,et al.  The Theory and Practice of Concurrency , 1997 .

[9]  Kaustav Banerjee,et al.  Interconnect limits on gigascale integration (GSI) in the 21st century , 2001, Proc. IEEE.

[10]  Alexandre Yakovlev,et al.  Moving from Weakly Endochronous Systems to Delay-Insensitive Circuits , 2005, FMGALS@MEMOCODE.

[11]  Alberto L. Sangiovanni-Vincentelli,et al.  Coping with Latency in SOC Design , 2002, IEEE Micro.

[12]  Amar Bouali,et al.  XEVE, an ESTEREL Verification Environment , 1998, CAV.

[13]  Michael Mendler,et al.  A Compositional Semantic Theory for Synchronous Component-based Design , 2003, CONCUR.

[14]  Mario R. Casu,et al.  A new approach to latency insensitive design , 2004, Proceedings. 41st Design Automation Conference, 2004..

[15]  Steven M. Nowick,et al.  Applications of asynchronous circuits , 1999, Proc. IEEE.

[16]  Montek Singh,et al.  Generalized Latency-Insensitive Systems for GALS Architectures , 2003 .

[17]  Hemangee K. Kapoor,et al.  Controllable Delay-Insensitive Processes , 2007, Fundam. Informaticae.

[18]  C. A. R. Hoare,et al.  Communicating sequential processes , 1978, CACM.

[19]  Benoît Caillaud,et al.  Concurrency in synchronous systems , 2004, Proceedings. Fourth International Conference on Application of Concurrency to System Design, 2004. ACSD 2004..

[20]  Geert Jan Olsder,et al.  Synchronization and Linearity: An Algebra for Discrete Event Systems , 1994 .

[21]  Luca P. Carloni.  The Role of Back-Pressure in Implementing Latency-Insensitive Systems , 2006, Electron. Notes Theor. Comput. Sci..

[22]  Scott Hauck,et al.  Asynchronous design methodologies: an overview , 1995, Proc. IEEE.

[23]  Alberto L. Sangiovanni-Vincentelli,et al.  Theory of latency-insensitive design , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[24]  Steve A. Schneider,et al.  Concurrent and Real-time Systems: The CSP Approach , 1999 .

[25]  Rance Cleaveland,et al.  An Algebraic Theory of Multiple Clocks , 1997, CONCUR.

[26]  Steven M. Nowick,et al.  Scanning the Technology Applications of Asynchronous Circuits , 1999 .

[27]  Hemangee K. Kapoor,et al.  Formal Modelling and Verification of an Asynchronous DLX Pipeline , 2006, Fourth IEEE International Conference on Software Engineering and Formal Methods (SEFM'06).

[28]  Hemangee K. Kapoor,et al.  Modelling Latency-Insensitive Systems in CSP , 2007, Seventh International Conference on Application of Concurrency to System Design (ACSD 2007).

[29]  C. Petri.  Kommunikation mit Automaten , 1962 .

[30]  Jordi Cortadella,et al.  Synthesis of synchronous elastic architectures , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[31]  Steven M. Nowick,et al.  An introduction to asynchronous circuit design , 1998 .

[32]  Cheng-Kok Koh,et al.  Performance analysis of latency-insensitive systems , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[33]  Alberto L. Sangiovanni-Vincentelli,et al.  A methodology for correct-by-construction latency insensitive design , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[34]  Jordi Cortadella,et al.  Synchronous Elastic Networks , 2006, 2006 Formal Methods in Computer Aided Design.

[35]  Julien Boucaron,et al.  Another Glance at Relay Stations in Latency-Insensitive Design , 2005, FMGALS@MEMOCODE.

[36]  Steven M. Nowick,et al.  Robust interfaces for mixed-timing systems , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[37]  Tadao Murata,et al.  Petri nets: Properties, analysis and applications , 1989, Proc. IEEE.

[38]  Charles André.  Representation and Analysis of Reactive Behaviors: A Synchronous Approach , 2000 .

[39]  Michael Mendler,et al.  An Asynchronous Algebra with Multiple Clocks , 1994, ESOP.