High-Throughput QC-LDPC Decoders

High-throughput design approaches for quasi-cyclic (QC) low-density parity-check (LDPC) decoders are presented in this paper. Three novel schemes for the horizontal process in min-sum algorithm and its revisions are derived to reduce design and implementation complexity. The schemes can be directly applied for variant QC codes and easily pipelined to increase the operating frequency of the decoder. Some improvements of the semi-parallel architecture are proposed to enhance throughput performance and hardware efficiency. Employing the proposed approaches, QC-LDPC decoders for Chinese Digital Television Terrestrial Broadcasting (DTTB) standard are implemented using field programmable gate array (FPGA). As shown in the results, the proposed approaches can substantially improve the throughput performance, as well as the throughput-and-hardware tradeoff, of decoders with semi-parallel architecture.

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