Slave controller for parallel operation inverter system

The present invention relates to a slave controller which communicates a master controller and controls an inverter in a parallel operation inverter system. The present invention comprises a first adding unit, a PI control unit, a remitter, and a second adding unit. The first adding unit calculates an error between a phase output current and an average value for each three phase output current. The PI control unit calculates a compensation pulse width for each phase by using the error of each phase calculated in the first adding unit. The remitter limits the pulse width compensated in the PI control unit within a constant range. The second adding unit adds the compensation pulse width of each phase outputted in the remitter to an original pulse width for a corresponding phase. The present invention is provided to equally flow in an output current of an inverter by following an output current average value of each inverter and enable various inverters to distribute same power, thereby optimizing the design of the inverter parallel operation system. [Reference numerals] (21-1,21-2,21-3) First adding unit; (22-1,22-2,22-3) PI control unit; (23-1,23-2,23-3) Remitter; (24-1,24-2,24-3) Second adding unit