Design and implementation of an optimized FIR filter for IF GPS signal simulator

This paper presents the design and implementation of a forty-order FIR filter for IF GPS signal simulator with three algorithms: multiply and accumulate (MAC), add-and-shift scheme with CSD encoding (CSD), new common sub-expression elimination (CSE). Each scheme is analyzed in detail including design and optimization process to find the best one with the least hardware resource and power consumption. The FIR filter is coded in Verilog HDL, and then implemented using Xilinx Virtex5 FPGA and Design Compiler based on SMIC 0.18um technology. FPGA implementation result shows that CSE consumes the least total occupied slice, with 63% and 20% reduction compared with MAC and CSD. The implementation of CSE in ASIC also proves 66% and 13% reduction in total chip area, as well as 36% and 6% dynamic power reduction compared with MAC and CSD respectively.

[1]  David V. Anderson,et al.  Hardware-efficient distributed arithmetic architecture for high-order digital filters , 2005, Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005..

[2]  H. T. Nguyen,et al.  Number-splitting with shift-and-add decomposition for power and hardware optimization in linear DSP synthesis , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Koeng-Mo Sung,et al.  A novel approach for the equalization of low frequency response in the automotive space , 2003, 2003 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03)..

[4]  Tang Bin,et al.  Distributed Arithmetic for FIR Filter Design on FPGA , 2007, 2007 International Conference on Communications, Circuits and Systems.

[5]  Mitsuru Yamada,et al.  A high-speed FIR digital filter with CSD coefficients implemented on FPGA , 2001, ASP-DAC '01.

[6]  Chip-Hong Chang,et al.  Efficient algorithms for common subexpression elimination in digital filter design , 2004, 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[7]  W. Neville Holmes,et al.  Binary Arithmetic , 2007, Computer.

[8]  Chiang-Ju Chien,et al.  A novel common-subexpression-elimination method for synthesizing fixed-point FIR filters , 2004, IEEE Trans. Circuits Syst. I Regul. Pap..

[9]  A. Prasad Vinod,et al.  A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Lei Dong,et al.  IF GPS Signal Simulator Development and Verification , 2003 .

[11]  Ryan Kastner,et al.  FPGA Implementation of High Speed FIR Filters Using Add and Shift Method , 2006, 2006 International Conference on Computer Design.

[12]  Chein-Wei Jen,et al.  A novel recursive digital filter based on signed digit distributed arithmetic , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[13]  R. Hartley.  Subexpression sharing in filters using canonic signed digit multipliers , 1996 .

[14]  Patrick Schaumont,et al.  A new algorithm for elimination of common subexpressions , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Xing Zhang,et al.  The implementation methods of high speed FIR filter on FPGA , 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

[16]  George W. Reitwiesner,et al.  Binary Arithmetic , 1960, Adv. Comput..

[17]  Kaushik Roy,et al.  High-performance FIR filter design based on sharing multiplication , 2003, IEEE Trans. Very Large Scale Integr. Syst..