Behavioral VHDL Styles and High-Level Synthesis for IPs

The recent emerging of commercial high-level synthesis tools raises the question of specifying IPs at the algorithmic, or behavioral, level. High-level synthesis allows fast exploration of various architectural solutions from a single behavioral description. While flexibility of currently used soft IPs is limited to optimizing the logic synthesis flow, behavioral IPs introduce architectural flexibility and allow a closer adaptation to the requirements of a target application. Since reusing code at the behavioral level may be hazardous due to the high abstraction level of the specification, a methodology should be defined in order to provide a framework for ensuring synthesizability of a behavioral IP, performance predictability and toolindependence of the specification. Formalizing the syntax, behavioral semantics and architectural semantics of commercial HLS tools is the first step for defining such a methodology. In this paper, we introduce the first results of an experiment consisting of analyzing the architectural model of a commercial HLS tool.