Improved Redundant Binary Adder Realization in FPGA

This paper presents the design of improved redundant binary adder (IRBA) by utilizing positive–negative encoding rules in FPGA platform. The proposed design deals with inverted encoding of negative binary (IEN) and positive binary number to get addition result using readily available standard hardware module. The Verilog hardware description language is used as design entry for synthesis of the proposed architecture in Xilinx ISE Desisn Suite 14.4 software. This structure is realized on Vertex-4 xc4vfx12-12sf363 FPGA device. The proposed IRBA is found to be time efficient in comparison with the performance parameters such as propagation delay and area over previous reported architecture.