Compact low-power implementation for continuous-time ΣΔ modulators

This paper presents a low-area continuous time (CT) sigma-delta (@S@D) modulator implementation based on a local feedback. The proposed structure provides a very low impedance node without the need of classical op-amps, which leads to a reduction in power and area consumption. Two versions of a conventional first-order CT @S@D modulator prototype have been fabricated with the purpose of evaluating the idea. The modulator requirements have been set for a passive RFID tag with sensing capability application, so that achieving minimum active area and very low power consumption are the main objectives for the presented design. Experimental results of the first version of the modulator show 8 bits of Effective-Number-Of-Bits (ENOB) in a 25kHz signal bandwidth with 7@mW of power consumption. The proposed implementation has also shown to be very robust against supply voltage and bias current variations. A second approach has also been designed, using the same principle of operation, in order to increase the input voltage range without any power consumption penalty at the expense of decreasing the input impedance and stingily increased area. This second approach shows 9 bits of ENOB in the same signal bandwidth with a power consumption of 4.35@mW. A Figure Of Merit (FOM) of 0.267pJ/state has been achieved with a total area consumption (without pads) of 110@mmx125@mm in a 0.35@mm CMOS technology.

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