Race a word-level atpg-based constraints solver system for smart random simulation

Functional verijication of complex designs largely relies on the use of simulation in conjunction high-level verijication languages (HVL) and test-bench automation (TBA) tools. In a constraints-based verification methodology, constraints are used to model the environmental restrictions of the Design Under Verification (DUV), and are specijied using HVL constructs. The job of a constraints solver is to produce multiple random solutions to these constraints. These random solutions are used to drive legal random stimulus to the DUV using procedural HVL constructs.

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