A Low-Noise Four-Stage Voltage-Controlled Ring Oscillator in Deep-Submicrometer CMOS Technology

This brief presents a low-voltage and low-noise ring voltage-controlled oscillator (VCO) where the phase noise performance is improved by reducing the total channel thermal noise injected into the output node of the VCO during the transition period of the output voltage swing. Implemented in a 65-nm CMOS technology, the proposed ring VCO operates from 485.7 to 1011.6 MHz. At 645 MHz, the measured phase noise is <formula formulatype="inline"><tex Notation="TeX">$-$ </tex></formula>110.8 dBc/Hz at an offset of 1 MHz while dissipating 10 mW from a 1-V supply.

[1]  Revna Acar Vural,et al.  International Journal of Electronics and Communications (aeü) Analog Circuit Sizing via Swarm Intelligence , 2022 .

[2]  M. A. Gaikwad,et al.  Area Efficient Wide Frequency Range CMOS Voltage Controlled Oscillator For PLL In 0 . 18 μm CMOS Process , 2012 .

[3]  Ganapati Panda,et al.  Effects of finite register length on fast ICA, bacterial foraging optimization based ICA and constrained genetic algorithm based ICA algorithm , 2010, Digit. Signal Process..

[4]  Jeevan Kanesan,et al.  Design of Low-phase Noise, Low-power Ring Oscillator for OC-48 Application , 2012 .

[5]  Rob A. Rutenbar,et al.  Optimal Design of a CMOS OpAmp via Geometric Programming , 2002 .

[6]  Kyutae Lim,et al.  A ring VCO with wide and linear tuning characteristics for a cognitive radio system , 2008, 2008 IEEE Radio Frequency Integrated Circuits Symposium.

[7]  Zoran Stamenkovic,et al.  A CMOS Voltage Controlled Ring Oscillator with Improved Frequency Stability , 2010 .

[8]  Magnus Jonsson,et al.  Towards Reliable Wireless Industrial Communication With Real-Time Guarantees , 2009, IEEE Transactions on Industrial Informatics.

[9]  Saraju P. Mohanty,et al.  Fast optimization of nano-CMOS voltage-controlled oscillator using polynomial regression and genetic algorithm , 2013, Microelectron. J..

[10]  Ganapati Panda,et al.  A Particle-Swarm-Optimization-Based Decentralized Nonlinear Active Noise Control System , 2012, IEEE Transactions on Instrumentation and Measurement.

[11]  Sujata Pandey.  Low Power Voltage Controlled Ring Oscillator Design with Substrate Biasing , .

[12]  Y. A. Eken,et al.  A 5.9-GHz voltage-controlled ring oscillator in 0.18-/spl mu/m CMOS , 2004, IEEE Journal of Solid-State Circuits.

[13]  Shyam Akashe,et al.  High performance of low voltage controlled ring oscillator with reverse body bias technology , 2013 .

[14]  Y. A. Eken,et al.  A 5.9-GHz Voltage-Controlled Ring Oscillator in 0.18- m CMOS , 2004 .

[15]  S. Akashe,et al.  Comparative Analysis of Schmitt Trigger with AVL (AVLG and AVLS) Technique Using Nanoscale CMOS Technology , 2013, 2013 Third International Conference on Advanced Computing and Communication Technologies (ACCT).

[16]  Shey-Shi Lu,et al.  A Single-VCO Fractional-$N$ Frequency Synthesizer for Digital TV Tuners , 2007, IEEE Transactions on Industrial Electronics.

[17]  Meie Shen,et al.  Optimizing RFID Network Planning by Using a Particle Swarm Optimization Algorithm With Redundant Reader Elimination , 2012, IEEE Transactions on Industrial Informatics.

[18]  Nidhi Thakur,et al.  Design of Low power, Low Jitter Ring Oscillator Using 50nm CMOS Technology , 2012 .

[19]  Shyam Akashe,et al.  Noise Sensitivity Analysis of 5 Stages Voltage Controlled Ring Oscillator at nm Technology , 2013 .

[20]  David E. Goldberg,et al.  Genetic Algorithms in Search Optimization and Machine Learning , 1988 .

[21]  Kim-Fung Man,et al.  Computational Optimization Algorithms for Antennas and RF/Microwave Circuit Designs: An Overview , 2012, IEEE Transactions on Industrial Informatics.

[22]  Andreas Willig,et al.  Recent and Emerging Topics in Wireless Industrial Communications: A Selection , 2008, IEEE Transactions on Industrial Informatics.

[23]  Howard C. Luong,et al.  A 900-MHz CMOS low-phase-noise voltage-controlled ring oscillator , 2001 .

[24]  Virendra Verma,et al.  Low Power Consumption Differential Ring Oscillator , 2013 .

[25]  Michiel Steyaert,et al.  A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors , 1997, IEEE J. Solid State Circuits.

[26]  Antonio Calomarde,et al.  All-Digital Simple Clock Synthesis Through a Glitch-Free Variable-Length Ring Oscillator , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[27]  Yeong-Her Wang,et al.  A 5 GHz Differential Colpitts CMOS VCO Using the Bottom PMOS Cross-Coupled Current Source , 2009, IEEE Microwave and Wireless Components Letters.

[28]  Srinivasa Vemuru,et al.  Short-circuit power dissipation estimation for cmos logic gates , 1994 .

[29]  Toru Nakura,et al.  Ring oscillator based random number generator utilizing wake-up time uncertainty , 2009, 2009 IEEE Asian Solid-State Circuits Conference.

[30]  Madhusmita Panda,et al.  Design and performance analysis of voltage controlled oscillator in CMOS technology , 2015, 2015 International Conference on Signal Processing and Communication (ICSC).

[31]  Devendra Kumar Gautam,et al.  Design a Low Power Half-Subtractor Using AVL Technique Based on 65nm CMOS Technology , 2013 .

[32]  Aniket Prajapati,et al.  Analysis of Current Starved VoltageControlled Oscillator using 45nm CMOSTechnology , 2014 .

[33]  Bosco H. Leung.  A Switching-Based Phase Noise Model for CMOS Ring Oscillators Based on Multiple Thresholds Crossing , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[34]  Günhan Dündar,et al.  Optimization Using a Modified Second-Order Approach With Evolutionary Enhancement , 2008, IEEE Transactions on Industrial Electronics.

[35]  Ali Hajimiri,et al.  A general theory of phase noise in electrical oscillators , 1998 .

[36]  Sushil Kumar,et al.  Design and Performance Analysis of Nine Stages CMOS Based Ring Oscillator , 2012, VLSIC 2012.

[37]  Bernard Huyart,et al.  A reconfigurable high-frequency phase-locked loop , 2004, IEEE Transactions on Instrumentation and Measurement.

[38]  Spiridon Nikolaidis,et al.  Propagation delay and short-circuit power dissipation modeling of the CMOS inverter , 1998 .

[39]  Tapabrata Ray,et al.  Performance of infeasibility driven evolutionary algorithm (IDEA) on constrained dynamic single objective optimization problems , 2009, 2009 IEEE Congress on Evolutionary Computation.

[40]  Tapabrata Ray,et al.  Infeasibility Driven Evolutionary Algorithm for Constrained Optimization , 2009 .

[41]  Vrushali G Nasre,et al.  A Performance Comparison of Current Starved VCO and Source Coupled VCO for PLL in 0 . 18 μ m CMOS Process , 2012 .

[42]  Han-Xiong Li,et al.  A Multiobjective Optimization Based Fuzzy Control for Nonlinear Spatially Distributed Processes With Application to a Catalytic Rod , 2012, IEEE Transactions on Industrial Informatics.

[43]  A.A. Abidi,et al.  Phase Noise and Jitter in CMOS Ring Oscillators , 2006, IEEE Journal of Solid-State Circuits.

[44]  Saraju P. Mohanty,et al.  Fast analog design optimization using regression-based modeling and genetic algorithm: A nano-CMOS VCO case study , 2013, International Symposium on Quality Electronic Design (ISQED).

[45]  Anna George,et al.  A Low Power Self-Healing VCO Using Frequency Divider for PLL , 2014 .

[46]  Hendrikus J. M. Veendrick,et al.  Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits , 1984 .

[47]  Tharam S. Dillon,et al.  Enhancement of Speech Recognitions for Control Automation Using an Intelligent Particle Swarm Optimization , 2012, IEEE Transactions on Industrial Informatics.

[48]  Mehul L. Patel,et al.  Low Power Wide Frequency Range Current Starved CMOS VCO in 180nm, 130nm and 90nm CMOS Technology , 2013 .

[49]  A.A. Abidi,et al.  High-frequency noise measurements on FET's with small dimensions , 1986, IEEE Transactions on Electron Devices.

[50]  Devendra Rani.  A Voltage Controlled Oscillator using Ring Structure in CMOS Technology , 2012 .

[51]  Masanori Hashimoto,et al.  A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

[52]  S. Akashe,et al.  Low power analysis in single stage source coupled VCO with AVL technique using nanoscale CMOS technology , 2013, 2013 Students Conference on Engineering and Systems (SCES).

[53]  S. A. Ladhake,et al.  HIGH PERFORMANCE VOLTAGE CONTROLLED OSCILLATOR (VCO) USING 65 NM VLSI TECHNOLOGY , 2010 .

[54]  Zuow-Zun Chen,et al.  The Design and Analysis of Dual-Delay-Path Ring Oscillators , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[55]  Beomsup Kim,et al.  A low-noise, 900-MHz VCO in 0.6-/spl mu/m CMOS , 1999 .

[56]  Dushan Boroyevich,et al.  Phase-Locked Loop Noise Reduction via Phase Detector Implementation for Single-Phase Systems , 2011, IEEE Transactions on Industrial Electronics.

[57]  Bogdan M. Wilamowski,et al.  A radiation-hard phase-locked loop , 2003, 2003 IEEE International Symposium on Industrial Electronics ( Cat. No.03TH8692).

[58]  Shuenn-Yuh Lee,et al.  Analysis and Implementation of a 0.9-V Voltage-Controlled Oscillator With Low Phase Noise and Low Power Dissipation , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[59]  J.G. Maneatis,et al.  Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[60]  A. Hajimiri,et al.  Jitter and phase noise in ring oscillators , 1999, IEEE J. Solid State Circuits.

[61]  Tapabrata Ray,et al.  Towards practical evolutionary robust multi-objective optimization , 2011, 2011 IEEE Congress of Evolutionary Computation (CEC).

[62]  Saraju P. Mohanty,et al.  Impact of gate-oxide tunneling on mixed-signal design and simulation of a nano-CMOS VCO , 2009, Microelectron. J..

[63]  Ali Jafari,et al.  A design automation system for CMOS analog integrated circuits using New Hybrid Shuffled Frog Leaping Algorithm , 2012, Microelectron. J..

[64]  A. A. Abidi,et al.  Wireless transceivers in CMOS IC technology. The new wave , 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).

[65]  Manoj Sachdev,et al.  A method to derive an equation for the oscillation frequency of a ring oscillator , 2003 .

[66]  M. Sachdev,et al.  An analytical equation for the oscillation frequency of high-frequency ring oscillators , 2004, IEEE Journal of Solid-State Circuits.

[67]  Saraju P. Mohanty,et al.  Design of Parasitic and Process-Variation Aware Nano-CMOS RF Circuits: A VCO Case Study , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[68]  Ganapati Panda,et al.  A Multiobjective Optimization Based Fast and Robust Design Methodology for Low Power and Low Phase Noise Current Starved VCO , 2014, IEEE Transactions on Semiconductor Manufacturing.

[69]  Aravind Seshadri,et al.  A FAST ELITIST MULTIOBJECTIVE GENETIC ALGORITHM: NSGA-II , 2000 .

[70]  Pei-Kang Tsai,et al.  Integration of Current-Reused VCO and Frequency Tripler for 24-GHz Low-Power Phase-Locked Loop Applications , 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

[71]  Sunil Kumar,et al.  Designing of High Speed Floating Gate Differential Ring RLC VCO with Error-Tracking MISO Filter for Low Noise Applications , 2015, 2015 Second International Conference on Advances in Computing and Communication Engineering.

[72]  Massimo Alioto,et al.  Oscillation frequency in CML and ESCL ring oscillators , 2001 .

[73]  Pradip Mandal,et al.  CMOS op-amp sizing using a geometric programming formulation , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..