Architecture of datapath-oriented coarse-grain logic and routing for FPGAs

In this paper, we propose a new datapath-oriented FPGA architecture that utilizes coarse-grain logic and routing resources to increase the area efficiency of datapath circuits. Using a set of custom-built datapath-oriented CAD tools and a set of datapath benchmarks, we investigated several variants of our proposed architecture. We found that the architecture achieves the highest area efficiency when 40% to 50% of the total routing tracks are coarse-grain. Furthermore, compared to conventional FPGA architectures, our datapath-oriented architecture uses about 10% less area to implement the same circuits.

[1]  Anshul Kumar,et al.  Direct mapping of RTL structures onto LUT-based FPGA's , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Thomas Kutzschebauch.  Efficient logic optimization using regularity extraction , 2000, Proceedings 2000 International Conference on Computer Design.

[3]  Jean Vuillemin,et al.  A reconfigurable arithmetic array for multimedia applications , 1999, FPGA '99.

[4]  Don Cherepacha,et al.  DP-FPGA: An FPGA Architecture Optimized for Datapaths , 1996, VLSI Design.

[5]  Guy Lemieux,et al.  On two-step routing for FPGAS , 1997, ISPD '97.

[6]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[7]  C. Zheng,et al.  ; 0 ; , 1951 .

[8]  Anshul Kumar,et al.  FAST: FPGA targeted RTL structure synthesis technique , 1994, Proceedings of 7th International Conference on VLSI Design.

[9]  Andreas Koch.  Module compaction in FPGA-based regular datapaths , 1996, DAC '96.

[10]  Andreas Koch.  Structured Design Implementation - A Strategy for Implementing Regular Datapaths on FPGAs , 1996, Fourth International ACM Symposium on Field-Programmable Gate Arrays.

[11]  Thomas Kutzschebauch,et al.  Regularity driven logic synthesis , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[12]  John Wawrzynek,et al.  Fast module mapping and placement for datapaths in FPGAs , 1998, FPGA '98.

[13]  Miodrag Potkonjak,et al.  Performance optimization using template mapping for datapath-intensive high-level synthesis , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Jonathan Rose,et al.  Synthesizing datapath circuits for FPGAs with emphasis on area minimization , 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..