COTS - radiation effects approaches and considerations

The downscaling in VLSI systems and the use of new materials influences the reliability of components in terms of radiation more and more. The unavoidable presence of particle radiation on ground and in space leads to unwanted failures in the electronic devices. Concerning packaging materials, design and technology a lot of steps were done to avoid radiation sensitivity. Nowadays microelectronic for automotive systems are tested to withstand radiation especially SEU-single event upsets. Especially since the Toyota Prius problem [1] it is clear that SEU cannot be ignored. Another application are unmanned autonomous vehicles and systems. Nevertheless reliability testing is expensive and extreme time consuming. The use of COTS-Commercials of the shelf is the ultimate goal to reach. In this paper an overview about the main influences concerning radiation hardness and COTS will be discussed. Furthermore different simulation approaches will be presented and discussed.

[2]  F. Wrobel,et al.  Natural radioactivity consideration for high-κ dielectrics and metal gates choice in nanoelectronic devices , 2010 .

[3]  J. Barak,et al.  Ion-track structure and its effects in small size volumes of silicon , 2002 .

[4]  Lahcen Hamouche.  Design of SRAM for CMOS 32nm , 2011 .

[5]  K. Barla,et al.  Integration of Fluorine-doped Silicon oxide in copper pilot line for 0.12-µm technology , 2002 .

[6]  J.W. Howard,et al.  Role of heavy-ion nuclear reactions in determining on-orbit single event error rates , 2005, IEEE Transactions on Nuclear Science.

[7]  R.C. Baumann,et al.  Radiation-induced soft errors in advanced semiconductor technologies , 2005, IEEE Transactions on Device and Materials Reliability.

[8]  S. Levine.  Alpha Emission Measurements of Lids and Solder Preforms on Semiconductor Packages , 1979 .

[9]  Jae Pil Jung,et al.  SOFT ERROR ISSUE AND IMPORTANCE OF LOW ALPHA SOLDERS FOR MICROELECTRONICS PACKAGING , 2013 .

[10]  R. Baumann,et al.  Neutron-induced boron fission as a major source of soft errors in deep submicron SRAM devices , 2000, 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059).

[11]  R.A. Reed,et al.  The effect of metallization Layers on single event susceptibility , 2005, IEEE Transactions on Nuclear Science.

[12]  Pia Sanda,et al.  Soft Errors: Technology Trends, System Effects, and Protection Techniques , 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

[13]  David Blaauw,et al.  A 128kb high density portless SRAM using hierarchical bitlines and thyristor sense amplifiers , 2011, 2011 12th International Symposium on Quality Electronic Design.

[14]  M. Turowski,et al.  Mixed-Mode Simulation and Analysis of Digital Single Event Transients in Fast CMOSICs , 2007, 2007 14th International Conference on Mixed Design of Integrated Circuits and Systems.

[15]  S.C. Sun,et al.  Process technologies for advanced metallization and interconnect systems , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[16]  M. Turowski,et al.  Single event upset modeling with nuclear reactions in nanoscale electronics , 2008, 2008 15th International Conference on Mixed Design of Integrated Circuits and Systems.

[17]  T.C. May,et al.  Measurement of Alpha Particle Radioactivtiy in IC Device Packages , 1979, 17th International Reliability Physics Symposium.

[18]  R. Gaillard,et al.  Investigation of Thermal Neutron Induced Soft Error Rates in Commercial Srams with 0.35 μm to 90 nm Technologies , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[19]  Xing Zhang,et al.  Novel devices and process for 32 nm CMOS technology and beyond , 2008, Science in China Series F: Information Sciences.

[20]  Tsai-Sheng Gau,et al.  Novel 20nm hybrid SOI/bulk CMOS technology with 0.183/spl mu/m/sup 2/ 6T-SRAM cell by immersion lithography , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..