Impact of Version Management for Transactional Memories on Phase-Change Memories

Two of the major issues in current computer systems are energy consumption and how to explore concurrent systems in a correct and efficient way. Solutions for these hazards may be sought both in hardware and in software. Phase-Change Memory (PCM) is a memory technology intended to replace DRAMs (Dynamic Random Access Memories) as the main memory, providing reduced static power consumption. Their main problem is related to write operations that are slow and wear their material. Transactional Memories are synchronization methods developed to reduce the limitations of lock-based synchronization. Their main advantages are related to being high-level and allowing composition and reuse of code, besides the absence of deadlocks. The objective of this study is to analyze the impact of different versioning managers (VMs) for transactional memories in PCMs. The lazy versioning/lazy acquisition scheme for version management presented the lowest wear on the PCM in 3 of 7 benchmarks analyzed, and results similar to the alternative versioning for the other 4~benchmarks. These results are related to the number of aborts of VMs, where this VM presents a much smaller number of aborts than the others, up to 39 times less aborts in the experiment with the benchmark Kmeans with 64 threads.

[1]  Maurice Herlihy,et al.  Transactional Memory: Architectural Support For Lock-free Data Structures , 1993, Proceedings of the 20th Annual International Symposium on Computer Architecture.

[2]  Harish Patil,et al.  Pin: building customized program analysis tools with dynamic instrumentation , 2005, PLDI '05.

[3]  Energy-Aware Microprocessor Synchronization : Transactional Memory vs . Locks , 2006 .

[4]  Mark Moir,et al.  Efficient nonblocking software transactional memory , 2007, PPOPP.

[5]  Torvald Riegel,et al.  Dynamic performance tuning of word-based software transactional memory , 2008, PPoPP.

[6]  Kunle Olukotun,et al.  STAMP: Stanford Transactional Applications for Multi-Processing , 2008, 2008 IEEE International Symposium on Workload Characterization.

[7]  A. Baldassin,et al.  Explorando memoria transacional em software nos contextos de arquiteturas assimetricas, jogos computacionais e consumo de energia , 2009 .

[8]  Hyunjin Lee,et al.  Flip-N-Write: A simple deterministic technique to improve PRAM write performance, energy and endurance , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[9]  Xiaolong Wu,et al.  Non-volatile Memory Devices Based on Chalcogenide Materials , 2009, 2009 Sixth International Conference on Information Technology: New Generations.

[10]  James R. Larus,et al.  Transactional Memory, 2nd edition , 2010, Transactional Memory.

[11]  Rami G. Melhem,et al.  Increasing PCM main memory lifetime , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[12]  Jun Yang,et al.  Phase-Change Technology and the Future of Main Memory , 2010, IEEE Micro.

[13]  Caio Hoffman,et al.  Análise de desgaste de técnicas de correção de erros em phase-change memories , 2013 .

[14]  Yifeng Zhu,et al.  Accelerating write by exploiting PCM asymmetries , 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

[15]  Rami G. Melhem,et al.  Bit mapping for balanced PCM cell programming , 2013, ISCA.

[16]  Daniel Mossé,et al.  Profiling Patterns of Bit Flipping for Software Transactional Memories , 2014, 2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing.

[17]  Jin Xiong,et al.  A Survey of Phase Change Memory Systems , 2015, Journal of Computer Science and Technology.

[18]  Zhiping Jia,et al.  A three-stage-write scheme with flip-bit for PCM main memory , 2015, The 20th Asia and South Pacific Design Automation Conference.

[19]  Daniel Mossé,et al.  Impact of Version Management on Transactional Memories' Performance , 2015, 2015 International Symposium on Computer Architecture and High Performance Computing Workshop (SBAC-PADW).