A compressed implementation of neural network with finite physical quantities on FPGAs
暂无分享,去创建一个
This paper presents the implementation of a multilayer neural network with finite physical quantities on a FPGA. The FPGA implementation extensively reduces much computer time for the neural network that requires iterative operation to exchange the physical quantities between neurons little by little.
[1] Xin Yao,et al. The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing , 1999, IEEE Trans. Computers.