GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay

This study has demonstrated that the clock tree construction in an SoC should be expanded to consider the intrinsic delay and skew of each IP's clock sink. A novel algorithm, called GDME, is proposed to combine grey relational clustering and DME approach for solving the problem of clock tree construction. Grey relational analysis can cluster the best pair of clock sinks and that guide a tapping point search for a DME algorithm for constructing a clock tree with zero skew and minimal delay. Experimentally, the proposed algorithm always obtains an RC-or RLC-based clock tree with zero skew and minimal delay for all the test cases and benchmarks. Experimental results demonstrate that the GDME improves up to 3.74% for total average in terms of total wire length compared with other DME algorithms. Furthermore, our results for the zero-skew RLC-based clock trees compared with Hspice are 0.017% and 0.2% lower for absolute average in terms of skew and delay, respectively.

[1]  Andrew B. Kahng,et al.  On the Bounded-Skew Clock and Steiner Routing Problems , 1995, 32nd Design Automation Conference.

[2]  Andrew B. Kahng,et al.  Planar-DME: a single-layer zero-skew clock tree router , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Asim J. Al-Khalili,et al.  Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  D. Al-Khalili,et al.  Area minimization of clock distribution networks using local topology modification , 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

[5]  Jason Cong,et al.  Bounded-skew clock and Steiner routing , 1998, TODE.

[6]  Yao-Wen Chang,et al.  Timing modeling and optimization under the transmission line model , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Xuan Zeng,et al.  Automatic clock tree design with IPs in the system , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[8]  Yehea I. Ismail,et al.  Effects of inductance on the propagation delay and repeater insertion in VLSI circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[9]  Cheng-Kok Koh,et al.  UST/DME: a clock tree router for general skew constraints , 2000, TODE.

[10]  Cheng-Kok Koh,et al.  Routability-driven repeater block planning for interconnect-centricfloorplanning , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Arvind Srinivasan,et al.  Clock routing for high-performance ICs , 1991, DAC '90.

[12]  Ren-Song Tsay,et al.  An exact zero-skew clock routing algorithm , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[14]  Yao-Wen Chang,et al.  RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[15]  J. Deng,et al.  Introduction to Grey system theory , 1989 .

[16]  Yehea I. Ismail,et al.  Equivalent Elmore delay for RLC trees , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..