Effect Of Charging On Pattern Placement Accuracy In E-Beam Lithography

An analysis of overlay measurements for wafers patterned by direct write lithography suggested that resist charging during electron beam exposure can produce significant pattern placement errors. This paper investigates the effect of charging for each critical level in Si processing and demonstrates how errors due to charging can be eliminated. A methodology employing Market measurements was used to provide statistically significant data on electron beam deflection. Charge accumulation in large exposed areas was found to produce offsets in the placement of registration crosses. Typical placement errors for a trilevel resist structure were 0.25 micron. Experiments showed that the magnitude of deflection was comparable for all substrate types, but increased with increasing trilevel resist thickness. These results are explained with a theoretical model which uses a Monte Carlo calculation to compute the dipole moments produced by accumulated charge. Various techniques to minimize the effect of charging were investigated. It was shown that in-creasing the electron accelerating voltage reduces beam deflection. In fact, pattern placement errors were made negligible by increasing the beam energy from 20 keV to 50 keV. In addition, both Ar ion implantation of the trilevel resist and the use of a metal trilevel structure were demonstrated to eliminate the effect of charging.