论文信息 - A cost-efficient 0.18 /spl mu/m CMOS RF transceiver using a fractional-N synthesizer for 802.11b/g wireless LAN applications

A cost-efficient 0.18 /spl mu/m CMOS RF transceiver using a fractional-N synthesizer for 802.11b/g wireless LAN applications

A single-chip 2.4 GHz, zero-IF transceiver for IEEE 802.11 b/g WLAN systems is fabricated on a 0.18 /spl mu/m CMOS technology. Based on an innovative system architecture using digital calibration, analog circuit imperfections are eliminated. The transceiver features enhanced phase noise performance with the use of a fractional-N synthesizer. A switched configuration allows for the same filters to be used on both TX/RX paths, thus minimizing area. It features a NF of 3.5 dB while the sensitivity is -78 dBm at 54 Mb/s operation, referred at the input of the chip. The transmit output 1 dB compression point is 9 dBm. Digital calibration helps achieve an EVM of -31 dB while transmitting -4 dBm at 54 Mb/s.

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