Compensation Strategies for Ramping Waveform of TPS Booster Synchrotron Main Power Supplies

Booster synchrotron for the Taiwan photon source project which is a 3 GeV synchrotron light source constructed at NSRRC had been commissioning successfully when the electron beam was accelerated to 3 GeV on December 16 2014. The booster is designed to ramp electron beams from 150 MeV to 3 GeV in 3 Hz therefore the large main power supplies have features of waveform play with trigger functionalities. However, due to the limited bandwidth of power supplies, different magnet loading will result in quite different phase lag for dipoles and four quadrupoles families and the relative err of input and output of dipole and quadrupoles would be quite different. To improve the relative error between the output readings and reference, several strategies are developed and will be summarized in this report. INTRODUCTION The TPS is a state-of-the-art synchrotron radiation facility featuring ultra-high photon brightness with extremely low emittance [1]. The 3 GeV stored electron beam with 5 mA was achieved and the first synchrotron light was observed in December 31. It consists of a 150 MeV electron Linac, a 3 GeV booster synchrotron, and a 3 GeV storage ring. The EPICS (Experimental Physics and Industrial Control System) was chosen for the TPS accelerator control. The booster main power supplies are composed of one dipole power supply with maximum current 1200 Ampere and four family quadrupole power supplies with maximum current of 120/150 Ampere. At first, these power supplies supported external trigger and internal waveform generator for booster power supply ramping. However, the reproducibility of power supply itself was unsatisfactory at injection due to non-synchronize and asynchronous internal clock of power supply regulator and external trigger. Therefore, the original digital regulation loop was modified to analogue and control interface was also revised so that all of power supplies could be driven by synchronized current waveform reference with common clock source and trigger. It effectively improved the reproducibility more than 1/5 [2, 3]. Figure 1 shows the overall booster ring power supplies control interface. One dedicated EPICS IOC equipped with one CPU blade, one EVR fanout and ADC/DAC modules is built to serve synchronous control and monitor of main booster power supply. Serial to Ethernet adapter are used to interface with On/Off control and status monitor. Moreover, the DT8837 which has 24 bits ADC provide extra high more precision monitoring than ADC modules and also support the external clock for synchronization.