Abstraction and BDDs Complement SAT-Based BMC in DiVer

Bounded Model Checking (BMC) based on Boolean Satisfiability (SAT) procedures has recently gained popularity for finding bugs in large designs. However, due to its incompleteness, there is a need to perform deeper searches for counterexamples, or a proof by induction where possible. The DiVer verification platform uses abstraction and BDDs to complement BMC in the quest for completeness. We demonstrate the effectiveness of our approach in practice on industrial designs.

[1]  P. Ashar,et al.  Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[2]  Stephan Merz,et al.  Model Checking , 2000 .

[3]  Sharad Malik,et al.  Exploiting Retiming in a Guided Simulation Based Validation Methodology , 1999, CHARME.

[4]  Kazutoshi Wakabayashi,et al.  Property-specific witness graph generation for guided simulation , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[5]  Helmut Veith,et al.  Automated Abstraction Refinement for Model Checking Large State Spaces Using SAT Based Conflict Analysis , 2002, FMCAD.

[6]  Gianpiero Cabodi,et al.  Improving SAT-based bounded model checking by means of BDD-based approximate traversals , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[7]  Kazutoshi Wakabayashi,et al.  Property-specific testbench generation for guided simulation , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[8]  R. P. Kurshan,et al.  Automata-theoretic verification of coordinating processes , 1994 .

[9]  Mary Sheeran,et al.  Checking Safety Properties Using Induction and a SAT-Solver , 2000, FMCAD.

[10]  Armin Biere,et al.  Symbolic Model Checking without BDDs , 1999, TACAS.

[11]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[12]  Kenneth L. McMillan,et al.  Symbolic model checking: an approach to the state explosion problem , 1992 .

[13]  Jason Baumgartner,et al.  Transformation-Based Verification Using Generalized Retiming , 2001, CAV.

[14]  Jacob A. Abraham,et al.  Property Checking via Structural Analysis , 2002, CAV.

[15]  Sharad Malik,et al.  Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).