A 5V-0nly 256K CMOS EEPROM using Barrier Height Lowering Technique

A 256k (32k × 8b) 5V-only EEPROM with high-density structure cell has been developed. The EEPROM, offering typically 150ns address access time, 80mW active, and 1¿W standby power dissipation, was successfully fabricated by a single-polysilicon and single metal CMOS process with a 1.2 ¿m photo lithography.

[1]  T. Sakurai,et al.  A 46ns 256K CMOS SRAM , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  S. Kohyama,et al.  Selective polysilicon oxidation technology for VLSI isolation , 1982, IEEE Transactions on Electron Devices.

[3]  T. Iizuka,et al.  A High Density Single-Poly Si Structure Eeprom with LB (Lowered Barrier Height) Oxide for VLSI's , 1985, 1985 Symposium on VLSI Technology. Digest of Technical Papers.

[4]  R. Cuppens,et al.  An EEPROM for microprocessors and custom logic , 1985, IEEE Journal of Solid-State Circuits.