IMPLEMENTATION OF DIGITAL COMPENSATORS

There are many techniques for designing discrete-time compensators. However, the digital implementation of such designs has not typically been addressed. The nature of digital hardware impacts the computational structure of the compensator and also can affect the original system design parameters. This paper deals with the architectural issues of serialism, parallelism and pipelining in implementing digital feedback compensators. The concepts of serialism and parallelism are shown to involve essentially the same considerationsfor digital compensators as for digital filters. However, the same cannot be said of pipelining, due to the feedback loop. A design technique is proposed for dealing with the problem of compensator pipelining, and several examples of pipelining LQG compensators are presented.