Dynamic Scheduling, Allocation, and Compaction Scheme for Real-Time Tasks on FPGAs

ii ACKNOWLEDGEMENTS I would like to express my heartfelt gratitude to Dr. Jerry L. Trahan for giving me his valuable guidance and insight during the course of this research work. I also acknowledge and appreciate the help rendered by Drs. Vaidyanathan Ramachandran, and Subhash C. Kak during the course of my graduate study. Thanks are also due to Dr. Susan Welsh of The Coastal Studies Institute for her constant support, encouragement and for also providing me with a graduate research assistantship. I would also like to thank my parents and my sister for their moral and academic support through all my academic endeavors. Finally, I would also like to thank all the graduate students of The Department of Electrical and Computer Engineering for making my stay in Baton Rouge a pleasant one.

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