Improving the Security of Dual-Rail Circuits

Dual-rail encoding, return-to-spacer protocol and hazard-free logic can be used to resist differential power analysis attacks by making the power consumption independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g. all-zeroes, which gives rise to power balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in each clock cycle regardless of the transmitted data values. To generate these dual-rail circuits an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the Advanced Encryption Standard (AES) have been simulated and compared in order to evaluate the method.

[1]  Victor I. Varshavsky,et al.  Self-Timed Control of Concurrent Processes , 1989 .

[2]  Ran Ginosar,et al.  An Efficient Implementation of Boolean Functions as Self-Timed Circuits , 1992, IEEE Trans. Computers.

[3]  Scott A. Brandt,et al.  NULL Convention Logic/sup TM/: a complete and consistent logic for asynchronous digital circuit synthesis , 1996, Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96.

[4]  Thomas S. Messerges,et al.  Investigations of Power Analysis Attacks on Smartcards , 1999, Smartcard.

[5]  Paul C. Kocher,et al.  Differential Power Analysis , 1999, CRYPTO.

[6]  William John Bainbridge,et al.  Delay insensitive system-on-chip interconnect using 1-of-4 data encoding , 2001, Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001.

[7]  Vincent Rijmen,et al.  The Design of Rijndael , 2002, Information Security and Cryptography.

[8]  George S. Taylor,et al.  Improving smart card security using self-timed circuits , 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.

[9]  Alex Kondratyev,et al.  Design of Asynchronous Circuits Using Synchronous CAD Tools , 2002, IEEE Des. Test Comput..

[10]  Siva Sai Yerubandi,et al.  Differential Power Analysis , 2002 .

[11]  Jim D. Garside,et al.  SPA - a synthesisable Amulet core for smartcard applications , 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.

[12]  I. Verbauwhede,et al.  A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards , 2002, Proceedings of the 28th European Solid-State Circuits Conference.

[13]  Sandra Dominikus,et al.  A Highly Regular and Scalable AES Hardware Architecture , 2003, IEEE Trans. Computers.

[14]  Mahmut T. Kandemir,et al.  Masking the energy behaviour of encryption algorithms , 2003 .

[15]  Alex Yakovlev,et al.  Balancing power signature in secure systems , 2003 .

[16]  Wei Zhang,et al.  Masking the energy behavior of DES encryption [smart cards] , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[17]  Luis A. Plana,et al.  An investigation into the security of self-timed circuits , 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..

[18]  Danil Sokolov,et al.  Improving the security of dual-rail circuits (revision 2) , 2004 .

[19]  Ingrid Verbauwhede,et al.  A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.