Design for Test and Diagnosis of Power Switches
暂无分享,去创建一个
Arnaud Virazel | Alberto Bosio | Luigi Dilillo | Patrick Girard | Miroslav Valka | Philippe Debaud | Stephane Guilhot
[1] W. Marsden. I and J , 2012 .
[2] Bashir M. Al-Hashimi,et al. High Quality Testing of Grid Style Power Gating , 2014, 2014 IEEE 23rd Asian Test Symposium.
[3] Arnaud Virazel,et al. Intra-Cell Defects Diagnosis , 2014, J. Electron. Test..
[4] Krishnendu Chakrabarty,et al. Delay Test for Diagnosis of Power Switches , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[5] Mohammad Tehranipoor,et al. Test of Power Management Structures , 2010 .
[6] Saibal Mukhopadhyay,et al. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.
[7] David Flynn,et al. Improved DFT for Testing Power Switches , 2011, 2011 Sixteenth IEEE European Test Symposium.
[8] Kaushik Roy,et al. Leakage power analysis and reduction: models, estimation and tools , 2005 .
[9] Sandeep Kumar Goel,et al. Testing and diagnosis of power switches in SOCs , 2006, Eleventh IEEE European Test Symposium (ETS'06).
[10] Vishwani D. Agrawal,et al. Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.