Constructive deterministic PRAM simulation on a mesh-connected computer

We present a constructive deterministic simulation of a PRAM with <italic>n</italic> processors and <italic>m</italic> = <italic>n</italic> <supscrpt>α</supscrpt> shared variables, 1 < α ≤ 2, on an <italic>n</italic>-node mesh-connected computer where each node hosts a processor and a memory module. At the core of the simulation is a Hierarchical Memory Organization Scheme (HMOS) that governs the distribution of the PRAM variables (each replicated into a number of copies) among the modules. The HMOS consists of a cascade of explicit bipartite graphs whose expansion properties, combined with suitable access and routing protocols, yield a time performance that, for α < 3/2, is close to the <inline-equation> <f> <g>W</g><fen lp="par"><rad><rcd><it>n</it></rcd></rad><rp post="par"></fen> </f> </inline-equation> bound imposed by the network's diameter, and that, for α ≥ 3/2, is a function of α never exceeding <inline-equation> <f> <ty><sc>O<fen lp="par"><it>n<sup><rm>5/8</rm></sup></it><rp post="par"></fen> </sc></ty></f> </inline-equation>.

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