Soft breakdown at all positions along the N-MOSFET

Abstract We observe soft breakdowns at all positions along the gates of N-MOSFETs when testing is performed at low voltage or with low current compliance. Devices whose breakdown spots are at or near the gate–drain overlap region have the highest off-currents, although not high enough to be fatal to device operation.

[1]  D. Hwang,et al.  Ultra-thin gate dielectrics: they break down, but do they fail? , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[2]  I. Eisele,et al.  Influence of soft breakdown on NMOSFET device characteristics , 1999, 1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296).

[3]  Guido Groeseneken,et al.  New insights in the relation between electron trap generation and the statistical properties of oxide breakdown , 1998 .

[4]  M. Alam,et al.  The statistical distribution of percolation resistance as a probe into the mechanics of ultra-thin oxide breakdown , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[5]  W. Abadeer,et al.  Structural dependence of dielectric breakdown in ultra-thin gate oxides and its relationship to soft breakdown modes and device failure , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[6]  A. Ghetti,et al.  Gate oxides in 50 nm devices: thickness uniformity improves projected reliability , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).