Low latency solver for linear equation systems in floating point arithmetic

Some applications, especially real time simulation systems, require to compute a linear system's solution in a very short amount of time. FPGA are well known to offer low latency computation and current chips are dense enough to implement hundreds of floating point operators. However, their many-stage pipelined architecture and the high cost of the divisors make the implementation of low latency applications a real challenge. We propose a division free algorithm founded on Gauss-Jordan algorithm, which takes advantage of the floating point format (any precision) and which exploits as much as possible the pipelined architecture of the operators. Results demonstrate that current FPGA can solve linear systems larger than hundred equations within ten microseconds in single or double precision arithmetic. This represents a two order of magnitude improvement over previous implementations.

[1]  Horácio C. Neto,et al.  On Reconfigurable Architectures for Efficient Matrix Inversion , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[2]  Carlos H. Llanos,et al.  FPGA implementation of large-scale matrix inversion using single, double and custom floating-point precision , 2012, 2012 VIII Southern Conference on Programmable Logic.

[3]  Carlos H. Llanos,et al.  FPGA HIL simulation of a linear system block for strongly coupled system applications , 2013, 2013 IEEE International Conference on Industrial Technology (ICIT).

[4]  Wei Zhang,et al.  Portable and scalable FPGA-based acceleration of a direct linear system solver , 2008, 2008 International Conference on Field-Programmable Technology.

[5]  Viktor K. Prasanna,et al.  Sparse Matrix Computations on Reconfigurable Hardware , 2007, Computer.

[6]  Shietung Peng,et al.  Parallel algorithm and architecture for two-step division-free Gaussian elimination , 1996, Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96.

[7]  Tarek Ould Bachir,et al.  General-purpose reconfigurable low-latency electric circuit and motor drive solver on FPGA , 2012, IECON 2012 - 38th Annual Conference on IEEE Industrial Electronics Society.

[8]  Habib Hamam,et al.  FPGA implementation of floating-point complex matrix inversion based on GAUSS-JORDAN elimination , 2013, 2013 26th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE).

[9]  Carlos H. Llanos,et al.  A fast and low cost architecture developed in FPGAs for solving systems of linear equations , 2012, 2012 IEEE 3rd Latin American Symposium on Circuits and Systems (LASCAS).

[10]  Jean Mahseredjian,et al.  Effective floating-point calculation engines intended for the FPGA-based HIL simulation , 2012, 2012 IEEE International Symposium on Industrial Electronics.

[11]  Mário P. Véstias,et al.  Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs , 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

[12]  Viktor K. Prasanna,et al.  Efficient Floating-point Based Block LU Decomposition on FPGAs , 2004, ERSA.

[13]  H.C. Neto,et al.  Memory Optimized Architecture for Efficient Gauss-Jordan Matrix Inversion , 2007, 2007 3rd Southern Conference on Programmable Logic.

[14]  D. Torres-Lucio,et al.  Array Processors Designed with VHDL for Solution of Linear Equation Systems Implemented in a FPGA , 2010, 2010 IEEE Electronics, Robotics and Automotive Mechanics Conference.