The design and implementation of DCT/IDCT chip with novel architecture

In the paper, an efficient VLSI architecture for a 8/spl times/8 two-dimensional discrete cosine transform and inverse discrete cosine transform (2-D DCT/IDCT) with a new 1-D DCT/IDCT algorithm is presented. The proposed new algorithm makes sure all coefficients are positive to simplify the design of multipliers and the coefficients have less round-off error than Lee's algorithm. For computing 2-D DCT/IDCT, the row-column decomposition method is used, and the design of 1-D DCT/IDCT requires only 9 multipliers and 21 adders/subtractors. This chip is synthesized with 0.6 /spl mu/m standard cell library and 1P3M CMOS technology, and it can be operated up to 100 MHz.